Semiconductor device and method for fabricating the same

ABSTRACT

The semiconductor device comprises a semiconductor substrate 10 , a conducting film 20 formed on the semiconductor substrate 10 and including two conductor patterns adjacent to each other; an etching stopper film covering the upper surface of the conducting film 20 ; an insulation film 28 which includes a contact hole which reaches the semiconductor substrate 10 between the two conductor patterns and the an end of which is positioned on the etching stopper film 22 on the two conductor patterns; and a sidewall insulation film 32 formed on the side walls of the conducting film 20 and of the etching stopper film 22 in the contact hole. The fluctuation of a contact hole size due to disalignment of the lithography can be restrained, and in the lithography step of opening the contact hole, the photoresist can have a large openings size, which facilitate the lithography step.

This application is a divisional of prior application Ser. No.:09/050,113 filed Mar. 30, 1998, the benefit of which is claimed under 35U.S.C. §120.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and a method forfabricating the same, more specifically to a semiconductor deviceincluding contact holes which are micronized suitably to be used in ahighly integrated DRAM and a method for fabricating the same.

As semiconductor devices are larger-scaled and higher-integrated, it isessential to micronize contact holes for interconnecting metallizationlayers. To this end various structures of semiconductor devices, whichpermit micronized contact holes to be formed, and various methods forfabricating semiconductor devices of the structures have been proposed.

Conventional semiconductor device fabricating methods which permitmicronized contact holes to be formed will be explained with referenceto FIGS. 47A-47C, 48A-48B, 49A-49C, 50A-50B, 51A-51D and 52A-52B. FIGS.47A-47C and 48A-48B are views explaining a first conventional method.FIGS. 49A-49C and 50A-50B are views explaining a second conventionalmethod. FIGS. 51A-51D and 52A-52B are views explaining a thirdconventional method.

In the first conventional method, two gate electrodes 204 are formedadjacent to each other on a silicon substrate 200 through a gateinsulation film 202.

Then, ions are implanted into the silicon substrate 200 with the gateelectrodes 204 as a mask to form an impurity diffused layer 206 in thesilicon substrate 200 on both sides of the gate electrodes 204.

Then, a silicon oxide film is deposited on the entire surface by, e.g.,CVD (Chemical Vapor Deposition) method, and the surface of the siliconoxide film is planarized to form an inter-layer insulation film 208 ofthe silicon oxide film (FIG. 47A).

A contact hole which reaches the impurity diffused layer 206 formed inthe silicon substrate 200 between the gate electrodes 204 is formed inthe inter-layer insulation film 208. First, the contact hole 210 isopened between the gate electrodes 204 by the usual lithography (FIG.47B), and then a silicon oxide film is grown on the entire surface, anda sidewall insulation film 212 of the contact hole 210 is formed byanisotropic etching which vertically advances (FIG. 47C).

In the first conventional method the contact hole 210 which thus arrivesat the impurity diffused layer 206 is formed, whereby the contact hole210 can have a size of below a resolution size limit.

The state shown in FIG. 47C is based on the assumption that nodisalignment takes place in the lithography step.

However, in the first conventional method when disalignment takes placein the lithography step for forming the contact hole, the gate electrode204 is often exposed in the contact hole 210 as shown in FIG. 48A. Inthis case, the disalignment is small, the gate electrodes 204 arecompletely covered with the sidewall insulation film 212, but when thedisalignment is large as shown in FIG. 48B, a surface of the gateelectrode 204 is exposed in the contact hole 210, and a metallizationlayer (not shown) formed in the contact hole 210 short-circuits with thegate electrode 204.

In view of this, in the second conventional method, as shown in FIGS.49A-49C, an etching stopper film 214 having etching characteristicsdifferent from those of the inter-layer insulation film 208 is inadvance formed on the gate electrodes 204.

In the thus fabricated semiconductor device if the contact hole 210 isextended over the gate electrode 204 by disalignment (FIG. 50A), thegate electrodes 204 are completely covered with the sidewall insulationfilm 212 and the etching stopper film 214, whereby short-circuit betweena metallization layer (not shown) formed in the contact hole 210 and thegate electrodes 204 can be prevented.

As means for forming a contact hole, the so-called SAC (self-alignedcontact) technique for opening a contact hole in self-alignment with agate electrode is known.

The third conventional method using the SAC technique will be explained.

First, a device isolation film 222 is formed on a silicon substrate 220.The device isolation film 222 is formed in, e.g., the staggeredarrangement as exemplified in FIG. 52A.

Then, a gate insulation film 224 is formed on the surface of the siliconsubstrate 220 by thermal oxidation.

Subsequently, a polycrystalline silicon film to be a gate electrode, anda silicon nitride film to be an etching stopper film are deposited onthe entire surface by, e.g., CVD method, and these films are processedin a pattern of the gate electrode. The gate electrode 226 with theupper surface covered with the etching stopper film 228 is thus formed(FIG. 51A).

Then, a silicon nitride film is deposited by, e.g, CVD method, andanisotropic etching in which the etching vertically advances isperformed to form a sidewall insulation film 230 on the side walls ofthe gate electrode 228 and the of the etching stopper film 228 (FIG.51B).

Next, a silicon oxide film is deposited by, e.g., CVD method, and thenthe surface of the silicon oxide film is planarized by, e.g., CMP(Chemical Mechanical Polishing) method to form an inter-layer insulationfilm 232 of the silicon oxide film (FIG. 51C).

Subsequently, a photoresist 234 having an opening having an opening on adevice region defined by the device isolation film 222 as shown in FIG.52B is formed, and the inter-layer insulation film 232 is etched withthe photoresist 234 as a mask (FIG. 50D).

For this etching, etching conditions which make an etching rate of thesilicon nitride film forming the etching stopper film 228 and thesidewall insulation film 230 sufficiently lower than an etching rate ofthe silicon oxide film forming the inter-layer insulation film 232 areselected, whereby the etching stopper film 228 and the sidewallinsulation film 230 in the photoresist 234 are not etched with theinter-layer insulation film 232 alone etched. That is, the contact hole236 can be opened in self-alignment with the gate electrode 224.

However, in the above-described first conventional method, as describedabove, the gate electrode 204 is often exposed in the contact hole 210due to disalignment of the lithography.

In the first and the second conventional methods, the contact hole oftenhas size fluctuations due to disalignment in the lithography step.

That is, without the disalignment, the ends of the contact hole isdefined by the sidewall insulation film 212 formed on the side walls ofthe inter-layer insulation film 208 as shown in FIGS. 47C and 49C. Whenthe disalignment takes place, however, as shown in FIGS. 48B and 50B,one end of the contact hole is defined by the sidewall insulation film212 formed on the side walls of the inter-layer insulation film 208, andthe other end of the contact hole is defined by the sidewall insulationfilm formed on the side walls of the gate electrode 204. Consequently,the contact hole often has a smaller size as the disalignment is larger.

In the third conventional method, the contact holes which are adjacentto each other with the gate electrode therebetween are formed inrespective patterns different from each other (FIG. 52B). This isbecause in forming in one pattern a plurality of contact holes adjacentto each other, in a case that plugs are buried in the respective contactholes by polishing, there is a high risk that the respective plugs maybe short-circuited with each other, and in isolating a conductor bylithography, there is an inconvenience that residues tend to take placeon the step of the contact hole, and the etching is thus very difficult.

However, in a case that as in the third conventional method, contactholes are very adjacent to each other, it is necessary that a hole sizein the photoresist formed by lithography is precise, and disalignmentcauses the above-described fluctuations of a contact hole size, andcontrol of disalignments must be strict.

In the third conventional method, the sidewall insulation film is formedmainly of silicon nitride film, but there is an inconvenience that thesidewall insulation film of silicon nitride film deteriorates hotcarrier immunity of a transistor than the sidewall insulation film ofsilicon oxide film.

It is empirically known that silicon nitride film formed on an inclinedportion has a higher etching rate than that formed on a flat portion. Inthe third conventional method, in which the inter-layer insulation filmis etched with the sidewall insulation film as a mask, an etchingselectivity for the silicon nitride film of the inclined region wherethe upper surface of the sidewall insulation film cannot be sufficientlyensured with a result that the gate electrode is often exposed in thecontact hole.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a semiconductor devicewhich allows an opening size of a photoresist to be less precise, haslittle fluctuation of a contact hole size due to disalignment oflithography, and has good resistance to hot carrier effect of atransistor, and a method for fabricating the semiconductor device.

The above-described object can be achieved by a semiconductor devicecomprising: a base substrate; a first conducting film formed on the basesubstrate and including two conductor patterns adjacent to each other;an etching stopper film covering an upper surface of the firstconducting film; a first insulation film which is an insulation-filmformed on the etching stopper film and the base substrate and includes acontact hole which reaches the base substrate between the two conductorpatterns and an end of which is positioned on the etching stopper filmon the conductor patterns; and a sidewall insulation film formed on sidewalls of the two conductor patterns of the first conducting film and ofthe etching stopper film on the two conductor patterns in the contacthole, whereby fluctuation of a contact hole size due to disalignment ofthe lithography can be restrained, and in the lithography step ofopening the contact hole, the photoresist can have a large openingssize, which facilitate the lithography step.

The above-described object can be also achieved by a semiconductordevice comprising: a base substrate; a first conducting film formed onthe base substrate and including a plurality of conductor patternsadjacent to each other; an etching stopper film covering an uppersurface of the first conducting film; a first insulation film which isan insulation film buried between said a plurality of conductor patternsand includes a contact hole which reaches the base substrate between theconductor patterns and having an end thereof defined by the conductorpatterns; and a sidewall insulation film formed on side walls of thefirst conducting film and of the etching stopper film in the contacthole, whereby fluctuation of a contact hole size due to disalignment ofthe lithography can be restrained, and in the lithography step ofopening the contact hole, the photoresist can have a large openingssize, which facilitate the lithography step.

In the above-described semiconductor device, it is preferable that aplurality of the contact holes are formed adjacent to each other withthe conductor patterns therebetween, whereby in a case that a pluralityof contact holes which are adjacent to each other with the conductorpatterns therebetween, it suffices to form a photoresist having oneopening including the contact regions, which permits the photoresist tohave a larger opening size in the lithography step of opening thecontact holes with a result that the lithography step can be simple.

In the above-described semiconductor device, it is preferable that thedevice further comprises: a second insulation film having a lowerdielectric constant than the etching stopper film between the firstconducting film and the etching stopper film. By providing the secondinsulation film of a lower dielectric constant, a parasitic capacitancebetween metallization layers can be smaller.

In the above-described semiconductor device, it is preferable that theetching stopper film is formed of conducting film. The present inventioncan be realized by forming the etching stopper film not only of aninsulation film but also a conducting film.

In the above-described semiconductor device, it is preferable that thedevice further comprises: a second conducting film formed on the firstinsulation film and connected to the base substrate in the contact hole,and wherein the etching stopper film is formed only in a region wherethe first conducting film intersects the second conducting film. In acase that the etching stopper film is formed in the conducting films, itis preferable that the etching stopper film is processed in the samepattern of the second conducting film so that the second conducting filmformed thereon is not short-circuited. Consequently, the etching stopperfilm is left in regions where the first conducting film intersects thesecond conducting film.

In the above-described semiconductor device, it is preferable that thesidewall insulation film is formed of a material having etchingcharacteristics substantially equal to those of the etching stopperfilm, and formed on an entire region of the side walls of the firstconducting film and the etching stopper film. The present invention isapplicable to the conventional semiconductor device having theconducting film covered with the etching stopper film, whereby thelithography step can be simple.

The above-described object can be also achieved by a semiconductordevice comprising: a semiconductor substrate; a plurality of word linesformed on the semiconductor substrate and extended in a first direction;an etching stopper film covering upper surfaces of the word lines; afirst insulation film which is an insulation film formed on the etchingstopper film and the semiconductor substrate and includes a contact holewhich reaches the semiconductor substrate between the word lines andhaving an end of which is positioned on the etching stopper film on theword lines; and a sidewall insulation film formed on side walls of theword lines and the etching stopper film in the contact hole. The contacthole structure of the present invention is applicable to bit linecontact holes of a DRAM (Dynamic Random Access Memory). Accordingly, infabrication process of the DRAM, fluctuation of a contact hole size dueto disalignment of the lithography can be restrained. In the lithographystep of opening the contact hole, the photoresist can have a largeopening size. Accordingly, the lithography step can be simple.

In the above-described semiconductor device, it is preferable that thedevice further comprises: a plug buried in the contact hole. By buryingthe plug in the contact hole, especially the storage electrode contacthole can have a low aspect ratio, which simplifies the etching step ofthe contact hole forming process.

The above-described object can be also achieved by a semiconductordevice comprising: a semiconductor substrate; a plurality of word linesformed on the semiconductor substrate and extended in a first direction;a first insulation film formed on the word lines and the semiconductorsubstrate; a plurality of bit lines formed on the first insulation filmand extended in a second direction which intersects the first direction;an etching stopper film covering upper surfaces of the bit lines; asecond insulation film which is an insulation film formed on the etchingstopper film and the first insulation film, and includes a contact holeformed between the bit lines and having an end thereof positioned on theetching stopper film on the bit lines; a-sidewall insulation film formedon side walls of the bit lines and the etching stopper film in thecontact hole; and a capacitor having one electrode connected to thesemiconductor substrate through the contact hole. The contact holestructure of the present invention is applicable to the storageelectrode contact hole of a DRAM. Accordingly, in fabrication process ofthe DRAM, fluctuation of a contact hole size due to disalignment of thelithography can be restrained. In the lithography step of opening thecontact hole, the photoresist can have a large opening size.Accordingly, the lithography step can be simple.

The above-described object can be also achieved by a semiconductordevice comprising: a semiconductor substrate; a plurality of word linesformed on the semiconductor substrate and extended in a first direction;a first insulation film formed on the word lines and the semiconductorsubstrate; a plurality of bit lines formed on the first insulation filmand extended in a second direction which intersects the first direction;an etching stopper film covering upper surfaces of the bit lines; asecond insulation film which is an insulation film buried between said aplurality of bit lines, and includes a contact hole formed between thebit lines and having an end thereof defined by the bit lines; a sidewallinsulation film formed on side walls of the bit lines and the etchingstopper film in the contact hole; and a capacitor having one electrodeconnected to the semiconductor substrate through the contact hole. Thecontact hole structure of the present invention is applicable to thestorage electrode contact hole of a DRAM. Accordingly, in fabricationprocess of the DRAM, fluctuation of a contact hole size due todisalignment of the lithography can be restrained. In the lithographystep of opening the contact hole, the photoresist can have a largeopening size. Accordingly, the lithography step can be simple.

In the above-described semiconductor device, it is preferable that saidone electrode of the capacitor is connected to the semiconductorsubstrate through a plug buried in the first insulation film. By buryingbeforehand the plug in the first insulation film, the storage electrodecontact hole can have a low aspect ratio, which simplifies the etchingfor forming the contact hole.

The above-described object can be achieved by a method for fabricating asemiconductor device comprising: a first conducting film forming step offorming on a base substrate a first conducting film including aplurality of conductor patterns adjacent to each other, and having anupper surface thereof covered with an etching stopper film; a firstinsulation film forming step of forming a first insulation film buriedbetween said a plurality of conductor patterns; a contact hole formingstep of etching the first insulation film with the etching stopper filmas a mask to form a contact hole which reaches the base substratebetween the conductor patterns and an end of which is defined by theconductor patterns; and a sidewall insulation film forming step forminga sidewall insulation film on side walls of the first conducting filmand the etching stopper film in the contact hole, whereby fluctuation ofa contact hole size due to disalignment of the lithography can berestrained, and in the lithography step of opening the contact hole, thephotoresist can have a large openings size, which facilitate thelithography step.

In the above-described method for fabricating the semiconductor device,it is preferable that in the contact hole forming step the firstinsulation film is etched with a photoresist having an opening extendedover said a plurality of conductor patterns and the etching stopper filmas a mask to form a plurality of the contact holes in the opening. Bythe etching by using as a mask a photoresist having an opening extendedover a plurality of conductor patterns, a plurality of contact holes canbe formed with the opening, which allows the photoresist to have a largeopening size in the lithography step of opening the contact holes. As aresult, the lithography step can be simple.

In the method for fabricating the semiconductor device, it is preferablethat the method further comprises before the first conducting filmforming step, a device isolation film forming step of forming a deviceisolation film buried in the base substrate. By forming the deviceisolation film by such trench isolation technique, the substrate can beretained flat even after the device isolation film is formed, which isvery effective to apply the contact hole forming technique of thepresent invention.

The above-described object can be also achieved by a method forfabricating a semiconductor device comprising: a word line forming stepof forming on a semiconductor substrate a plurality of word linesextended in a first direction and having upper surfaces thereof coveredwith an etching stopper film; a first insulation film forming step offorming a first insulation film on the etching stopper film and thesemiconductor substrate; a contact hole forming step of forming in thefirst insulation film a contact hole which reaches the semiconductorsubstrate between the word lines, and an end of which is positioned onthe etching stopper film on the word lines; a sidewall insulation filmforming step of forming a sidewall insulation film on side walls of theword lines and of the etching stopper film in the contact hole; and abit line forming step of forming on the first insulation film aplurality of bit lines extended in a second direction which intersectsthe first direction and connected to the semiconductor substrate throughthe contact hole. The present invention is applicable to the formingmethod of bit line contact holes of a DRAM. Accordingly, in fabricationprocess of the DRAM, fluctuation of a contact hole size due todisalignment of the lithography can be restrained. In the lithographystep of opening the contact hole, the photoresist can have a largeopening size. Accordingly, the lithography step can be simple.

The above-described object can be achieved by a method for fabricating asemiconductor device comprising: a word line forming step of forming ona semiconductor substrate a plurality of word lines extended in a firstdirection and having upper surfaces thereof covered with an etchingstopper film; a first insulation film forming step of forming a firstinsulation film buried between the word lines; a contact hole formingstep of etching the first insulation film with the etching stopper filmas a mask to form a contact hole which reaches the semiconductorsubstrate between the word lines and an end of which is defined by theword lines; a sidewall insulation film forming step of forming asidewall insulation film on side walls of the word lines and the etchingstopper film in the contact hole; and a bit line forming step of formingon the first insulation film a plurality of bit lines extended in asecond direction which intersects the first direction and connected tothe semiconductor substrate through the contact hole. The presentinvention is applicable to the method for fabricating the conventionalsemiconductor device having the conducting film covered with the etchingstopper film, whereby the lithography step can be simple.

The above-described object can be achieved by a method for fabricating asemiconductor device comprising: a word line forming step of forming ona semiconductor substrate a plurality of word lines extended in a firstdirection and having upper surfaces thereof covered with an etchingstopper film; a sidewall insulation film forming step of forming asidewall insulation film having etching characteristics substantiallyequal to those of the etching stopper film on side walls of the wordlines and of the etching stopper film; a first insulation film formingstep of forming a first insulation film buried between the word lineswith the sidewall insulation film formed on; a contact hole forming stepof etching the first insulation film with the etching stopper film andthe sidewall insulation film as a mask to form a contact hole whichreaches the semiconductor substrate between the word lines and an end ofwhich is defined by the sidewall insulation film; and a bit line formingstep of forming on the first insulation film a plurality of bit linesextended in a second direction which intersects the first direction andconnected to the semiconductor substrate through the contact hole. Thepresent invention is applicable to the forming method of bit linecontact holes of a DRAM. Accordingly, in fabrication process of the DRAMfluctuation of a contact hole size due to disalignment of thelithography can be restrained. In the lithography step of opening thecontact hole, the photoresist can have a large opening size.Accordingly, the lithography step can be simple.

In the method for fabricating the semiconductor device, it is preferablethat in the contact hole forming step, the first insulation film isetched with a photoresist including an opening extended over the wordlines, and the etching stopper film as a mask to form a plurality of thecontact holes in the opening. By the etching by using as a mask aphotoresist having an opening extended over a plurality of word lines aplurality of contact holes can be formed in the opening, which allowsthe photoresist to have a large opening size in the lithography step ofopening the contact holes. As a result, the lithography step can besimple.

In the method for fabricating the semiconductor device, it is preferablethat the method further comprises before the bit line forming step, aplug forming step of forming a plug buried in the contact hole. With thesurface of the substrate kept flat, the contact hole can be opened,which facilitates forming the buried plug in the contact hole.

The above-described object can be also achieved by a method forfabricating a semiconductor device comprising: a word line forming stepof forming on a semiconductor substrate a plurality of word linesextended in a first direction; a first insulation film forming step offorming a first insulation film on the semiconductor substrate with theword lines formed on; a bit line forming step of forming on the fistinsulation film a plurality of bit lines extended in a second directionwhich intersects the first direction and having upper surfaces thereofcovered with an etching stopper film; a second insulation film formingstep of forming a second insulation film on the etching stopper film andthe first insulation film; a contact hole forming step of forming in thesecond insulation film a contact hole which is formed between the bitlines and an end of which is positioned on the etching stopper film onthe bit lines; a sidewall insulation film forming step of forming asidewall insulation film on side walls of the bit lines and of theetching stopper film in the contact hole; and a capacitor forming stepof forming on the second insulation film a capacitor having oneelectrode connected to the semiconductor substrate through the contacthole. The present invention is applicable to the forming method of thestorage electrode contact hole of a DRAM. Accordingly, in fabricationprocess of the DRAM fluctuation of a contact hole size due todisalignment of the lithography can be restrained. In the lithographystep of opening the contact hole, the photoresist can have a largeopening size. Accordingly, the lithography step can be simple.

The above-described object can be also achieved by a method forfabricating a semiconductor device comprising: a word line forming stepof forming on a semiconductor substrate a plurality of word linesextended in a first direction; a first insulation film forming step offorming a first insulation film on the semiconductor substrate with theword lines formed on; a bit line forming step of forming on the firstinsulation film a plurality of bit lines extended in a second directionwhich intersects the first direction and having an upper surface thereofcovered with an etching stopper film; a second insulation film formingstep of forming a second insulation film buried between the bit lines; acontact hole forming step of etching the second insulation film with theetching stopper film as a mask to form a contact hole which is formed onbetween the bit lines and an end of which is defined by the bit lines; asidewall insulation film forming step of forming a sidewall insulationfilm on side walls of the bit lines and of the etching stopper film inthe contact hole; and a capacitor forming step of forming on the secondinsulation film a capacitor having one electrode connected to thesemiconductor substrate through the contact hole. The present inventionis applicable to the forming method of the storage electrode contacthole of a DRAM. Accordingly, in fabrication process of the DRAMfluctuation of a contact hole size due to disalignment of thelithography can be restrained. In the lithography step of opening thecontact hole, the photoresist can have a large opening size.Accordingly, the lithography step can be simple.

In the above-described method for fabricating the semiconductor device,it is preferable that in the contact hole forming step, the secondinsulation film is etched with a photoresist having a pattern whichalternately covers a region between the word lines, and the etchingstopper film as a mask to form a plurality of the contact holes. In thestorage electrode contact hole forming step, a plurality of contactholes can be opened by using the photoresist having stripe pattern whichalternately covers the regions between the word lines, the photoresistcan have a large opening size in the lithography step of opening thecontact holes. Accordingly, the lithography step can be simple.

In the above-described method for fabricating the semiconductor device,it is preferable that in the contact hole forming step, the firstinsulation film and the second insulation film are etched to form acontact hole which reaches the semiconductor substrate and an end ofwhich is defined by the bit lines and the word lines.

In the above-described method for fabricating the semiconductor device,it is preferable that in the bit line forming step, the etching stopperfilm is formed of a conductor; and in the capacitor forming step theetching stopper film is processed in the same pattern as said oneelectrode of the capacitor. In a case that the etching stopper film isformed of the conducting film, the etching stopper film is processed inthe same pattern as the storage electrode so that the storage electrodeformed thereon is not short-circuited.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagrammatic sectional view of the semiconductor deviceaccording to a first embodiment of the present invention, which shows astructure thereof.

FIGS. 2A-2D are sectional views of the semiconductor device according tothe first embodiment of the present invention in the steps of the methodfor fabricating the semiconductor device, which show the method.

FIGS. 3A and 3B are plan views of the semiconductor device according toa second embodiment of the present invention, which show a structurethereof.

FIG. 4 is a diagrammatic sectional view of the semiconductor deviceaccording to the second embodiment of the present invention, which showsa structure thereof.

FIGS. 5A-5C and 6A-6C are sectional views of the semiconductor deviceaccording to the second embodiment in the steps of the method forfabricating the semiconductor device, which show the method.

FIGS. 7A and 7B are plan views of the semiconductor device according toa third embodiment of the present invention, which show a structurethereof.

FIGS. 8A and 8B are diagrammatic sectional views of the semiconductordevice according to the third embodiment of the present invention, whichshow a structure thereof.

FIGS. 9A-9E, 10A-10C, 11A-11D and 12A-12C are sectional views of thesemiconductor device according to the third embodiment of the presentinvention in the steps of the method for fabricating the semiconductordevice, which show the method.

FIGS. 13A and 13B are plan views of a resist pattern for forming bitline contact holes of the semiconductor device according to the thirdembodiment of the present invention, and the opened contact holes.

FIGS. 14A and 14B are plan views of a resist pattern for forming storageelectrode contact holes of the semiconductor device according to thethird embodiment of the present invention, and the opened contact holes.

FIG. 15 is a diagrammatic sectional view of the semiconductor deviceaccording to a fourth embodiment of the present invention, which shows astructure thereof.

FIGS. 16A-16D and 17A-17B are sectional views of the semiconductordevice according to the fourth embodiment of the present invention inthe steps of the method for fabricating the semiconductor device, whichshow the method.

FIG. 18 is a diagrammatic sectional view of the semiconductor deviceaccording to a fifth embodiment of the present invention, which shows astructure thereof.

FIGS. 19A-19D and 20A-20C are sectional views of the semiconductordevice according to the fifth embodiment of the present invention in thesteps of the method for fabricating the semiconductor device, which showthe method.

FIG. 21 is a diagrammatic sectional view of the semiconductor deviceaccording to a sixth embodiment of the present invention, which shows astructure thereof.

FIGS. 22A-22E are sectional views of the semiconductor device accordingto the sixth embodiment of the present invention in the steps of themethod for fabricating the semiconductor device, which show the method.

FIGS. 23A and 23B are diagrammatic sectional views of the semiconductordevice according o a seventh embodiment of the present invention, whichshow a structure thereof.

FIGS. 24A-24E, 25A-25C, 26A-26E and 27A-27C are sectional views of thesemiconductor device according to the seventh embodiment of the presentinvention in the steps of the method for fabricating the semiconductordevice, which show the method.

FIGS. 28A and 28B are plan views of a resist pattern for forming bitline contact holes of the semiconductor device according to the seventhembodiment of the present invention, and the opened contact holes.

FIGS. 29A and 29B are plan views of a resist pattern for forming storageelectrode contact holes of the semiconductor device according to theseventh embodiment of the present invention, and the opened contactholes.

FIG. 30 is a plan view of a resist pattern for forming bit line contactholes of one modification of the semiconductor device according to theseventh embodiment of the present invention.

FIGS. 31A and 31B are diagrammatic sectional views of the semiconductordevice according to an eighth embodiment of the present invention, whichshow a structure thereof.

FIGS. 32A-32E, 33A-33C, 34A-34D and 35A-35C are sectional views of thesemiconductor device according to the eighth embodiment of the presentinvention in the steps of the method for fabricating the semiconductordevice, which show the method.

FIGS. 36A and 36B are diagrammatic sectional views of the semiconductordevice according to a ninth embodiment of the present invention, whichshow a structure thereof.

FIGS. 37A-37C, 38A-38B, 39A-39B, 40A-40C, 41A-41B and 42A-42B aresectional views of the semiconductor device according to the ninthembodiment of the present invention in the steps of the method forfabricating the semiconductor device, which show the method.

FIG. 43 is a diagrammatic sectional view of the semiconductor deviceaccording to one modification of the ninth embodiment of the presentinvention, which show a structure thereof.

FIG. 44 is a sectional view of the semiconductor device according to atenth embodiment of the present invention, which shows the structurethereof.

FIGS. 45A-45C and 46A-46C are sectional views of the semiconductordevice according to the tenth embodiment of the present invention in thesteps of the method for fabricating the semiconductor device, which showthe method.

FIGS. 47A-47C are sectional views of the first conventionalsemiconductor device in the steps of the method for fabricating thesemiconductor device, which show the method.

FIGS. 48A and 488 are views explaining the problems of the method forfabricating the first conventional semiconductor device.

FIGS. 49A-49C are sectional views of the second conventionalsemiconductor device in the steps of the method for fabricating thesemiconductor device, which show the method.

FIGS. 50A and 50B are views explaining the effect of the method forfabricating the second conventional semiconductor device.

FIGS. 51A-51D are sectional views of the third conventionalsemiconductor device in the steps of the method for fabricating thesemiconductor device, which show the method.

FIGS. 52A and 52B are plan views of a pattern layout used in the methodfor fabricating the third conventional semiconductor device.

FIG. 53 is a cross-sectional view along the extending direction of theconductor patterns of the semiconductor device according to the secondembodiment of the present invention, which shows a structure thereof.

DETAILED DESCRIPTION OF THE INVENTION

[A First Embodiment]

The semiconductor device and the method for fabricating thesemiconductor device according to a first embodiment of the presentinvention will be explained with reference to FIGS. 1 and 2A-2D.

FIG. 1 is a diagrammatic sectional view of the semiconductor deviceaccording to the present embodiment, which shows a structure thereof.FIGS. 2A-2D are sectional views of the semiconductor device according tothe present embodiment in the steps of the method for fabricating thesame, which show the method.

First, the structure of the semiconductor device according to thepresent embodiment will be explained with reference to FIG. 1.

Two gate electrodes 20 are formed adjacent to each other on a siliconsubstrate 10 through a gate insulation film 14. An etching stopper film22 of a silicon nitride film is formed on the gate electrodes 20.Impurity diffused layers 24, 26 are formed in the silicon substrate onboth sides of the gate electrodes 20. An inter-layer insulation film 28having a contact hole 30 opened on the impurity diffused layer 24 isformed on a MOSFET having this structure. A sidewall insulation film 32of a silicon oxide film is formed on the side walls of the inter-layerinsulation film 28 and the side walls of the gate electrode 20 and theetching stopper film 22 in the contact hole 30.

The semiconductor device according to the present embodiment ischaracterized in that the ends of the contact hole 30 formed in theinter-layer insulation film 28 are extended over the gate electrodes 20.Such contact hole provides various effects of facilitating thelithography step for forming the contact hole.

The semiconductor device according to the present embodiment is alsocharacterized in that the sidewall insulation film 32 is formed of asilicon oxide film.

Following the steps of the method for fabricating the semiconductordevice according to the present embodiment, the semiconductor deviceaccording to the present embodiment and the method for fabricating thesame will be explained.

First the silicon substrate 10 thermally oxidized to form the gateinsulation film 14 on the surface of the silicon substrate 10.

Then, a polycrystalline silicon film 16 is formed on the gate insulationfilm 14 by, e.g., CVD method. The polycrystalline silicon film 16 is tobe the gate electrodes 20.

Subsequently, a silicon nitride film 18 is deposited on thepolycrystalline silicon film 16 by, e.g., CVD method (FIG. 2A). Thesilicon nitride film 18 is to be the etching stopper film 22.

Then, the silicon nitride film 18 and the polycrystalline silicon film16 are processed in the same pattern to form the gate electrodes 20having the upper surfaces covered with the etching stopper film 22.

Then, e,g., phosphorus ions are implanted in the silicon substrate 10with the gate electrodes 20 as a mask to form the impurity diffusedlayers 24, 26 (FIG. 2B).

Subsequently, a silicon oxide film is deposited on the entire surfaceby, e.g., CVD method to form the inter-layer insulation film 28.

Then, a photoresist (not shown) having a pattern of the contact hole forexposing the impurity diffused layer 24 is formed by the usuallithography technique.

At this time, the photoresist is formed so that the ends of the contacthole are extended over the gate electrodes 20. This permits thelithography step to have a large alignment allowance, and facilitatesthe lithography step because it is not necessary to expose a fine holepattern.

Then, the inter-layer insulation film 28 is etched with the thus-formedphotoresist as a mask to open the contact hole 30 for exposing theimpurity diffused layer 24 (FIG. 2C).

The inter-layer insulation film 28 is etched under conditions whichprovide etching selectivity with respect to the etching stopper film 22.Thus, the contact hole 30 can be opened without damaging the gateelectrodes 20.

The photoresist is so arranged that the ends of the contact hole areextended over the gate electrodes 20 even when disalignment takes place,whereby even if disalignment takes place in forming the photoresist, anarea of the impurity diffused layer 24 exposed in the contact hole 30does not change. Accordingly, contact characteristics on the impuritydiffused layer 24 can be formed stable.

Even when etching conditions which provide etching selectivity withrespect to the etching stopper film 22, it has been empirically foundthat the reduction in the film thickness takes place on the etchingstopper film, e.g., the sidewall insulation film, which are not formedon the flat portion. In the method for fabricating the semiconductordevice according to the present embodiment, however, the etching stopperfilm 22 is formed only on the flat portions of the gate electrodes 20and the etching stopper film at the side wall portion is not necessary,whereby the contact hole 30 can be opened while the etching stopper film22 is prevented from the reduction in the film thickness.

Subsequently, a silicon oxide film is deposited on the entire surfaceby, e.g., CVD method, and then anisotropic etching, in which the etchingvertically advances, is used to form the sidewall insulation film 32 onthe side walls of the inter-layer insulation film 28, the gateelectrodes 20 and the etching stopper film 22 (FIG. 2D).

It is useful to grown an about 3 nm-thick oxide film by thermaloxidation before deposition of the above-described silicon oxide film torecover the gate oxide film on the ends of the gate electrodes frometching damages.

By thus forming the sidewall insulation film 32, the gate electrodes 20are covered with the silicon nitride film 22 and the sidewall insulationfilm 32 without being exposed in the contact hole 30.

It is unnecessary that the contact hole is opened by the self-alignmentin the sidewall insulation film 32, which allows the sidewall insulationfilm 32 to be formed of silicon oxide film. In comparison with theconventional semiconductor device in which the sidewall insulation film32 is formed of a silicon nitride film, the transistor can have higherhot carrier immunity.

Then, a metallization layer or a plug (not shown) are formed inconnection with the impurity diffused layer 24 through the contact hole30.

As described above, according to the present embodiment, the contacthole 30 for exposing the ends of the gate electrodes 20 are opened, andthen the sidewall insulation film 32 is formed on the side walls of thegate electrodes 20, whereby even if disalignment takes place in thelithography for opening the contact hole 30, an area of the contact onthe upper surface of the impurity diffused layer 24 never changes.Accordingly, the contact characteristics on the impurity diffused layer24 can be formed stable.

It is not necessary to form the contact hole by self-alignment with thesidewall insulation film formed on the side walls of the gateelectrodes, which permits the sidewall insulation film to be formed of asilicon oxide film. Accordingly in comparison with the conventionalsemiconductor device, whose sidewall insulation film is formed ofsilicon nitride film, the transistor can have higher hot carrierimmunity.

[A Second Embodiment]

The semiconductor device and a method for fabricating the same accordingto a second embodiment of the present invention will be explained withreference to FIGS. 3A-3B, 4, 5A-5C and 6A-6C.

FIGS. 3A and 3B are plan views of the semiconductor device according tothe present embodiment, which show a structure thereof. FIG. 4 is adiagrammatic sectional view of the semiconductor device according to thepresent embodiment, which shows the structure thereof. FIGS. 5A-5C and6A-6C are sectional views of the semiconductor device according to thepresent embodiment in the steps of the method for fabricating the same,which explain the method.

First, with reference to FIGS. 3A-3B and 4, the structure of thesemiconductor device according to the present embodiment will beexplained.

A device isolation film 12 for isolating devices is formed on a siliconsubstrate 10. Gate electrodes 20 are formed through a gate insulationfilm 14 on the silicon substrate 10 with the device isolation film 12formed on. The gate electrodes 20 are extended vertical of the sheet ofthe drawing, and as shown in FIG. 3A, two gate electrodes 20 are formedon each device region defined by the device isolation film 12. Aninsulation film 36 of a silicon oxide film, an etching stopper film 22of a silicon nitride film are formed on the gate electrodes 20. Impuritydiffused layers 24, 26 are formed in the silicon substrate 10 on bothsides of the gate electrodes 20. An inter-layer insulation film 28buried between the gate electrodes 20 having the upper surfaces coveredwith the insulation film 36 and the etching stopper film 22 to planarizethe surface of the substrate. As shown in FIG. 3B, an opening 38 forsurrounding the device region defined by the device isolation film 12 isformed in the inter-layer insulation film 28, and the inter-layerinsulation film 28 in the opening is removed. Thus, a contact hole 30 isopened on the impurity diffused layer 24, and contact holes 40 areformed on the impurity diffused layer 26. A sidewall insulation film 32is formed on the side walls of the contact holes 30, 40.

Then, the semiconductor device according to the present embodiment andthe method for fabricating the semiconductor device will be detailed inaccordance with the steps of the method for fabricating thesemiconductor device according to the present embodiment.

First, trenches are formed by the usual lithography in device isolationregion on, e.g., a p-type silicon substrate 10.

Then, a silicon oxide film is deposited by, e.g., CVD method, and thenthe surface of the silicon oxide film is polished to leave the siliconoxide film only in the trenches formed in the silicon substrate 10.Thus, the device isolation film 12 is formed, buried in the siliconsubstrate 10. The thus-formed device isolation film 12 is known astrench isolation. The device isolation film 12 may be formed by otherdevice isolation film forming techniques, such as LOCOS (LOCal Oxidationof Silicon), but the above-described trench isolation technique can makethe surface of the substrate flat, which facilitates burying plugs, forexample, and provides various conveniences in the later steps.

The device isolation film 12 is so formed that the device regions arestaggered arrangement as exemplified in FIG. 3A. The layout shown inFIG. 3A is one example of patterns applicable to memory cell regions ofa DRAM.

Subsequently, the silicon substrate 10 with the device isolation film 12formed on is thermally oxidized to form a gate insulation film 14 on thesurface of the silicon substrate 10.

Then, a polycrystalline silicon film 16 to be the gate electrodes 20 isdeposited on the gate insulation film 14 by, e.g., CVD method.

Next, an insulation film 36 of a silicon oxide film is deposited on thepolycrystalline silicon film 16 by, e.g., CVD method. As will bedetailed later, the insulation film 36 is not essential.

Subsequently, a silicon nitride film 18 to be the etching stopper film22 is deposited on the insulation film 16 by, e.g., CVD method (FIG.5A).

Then, the laminated film of the silicon nitride film 18, the insulationfilm 36 and the polycrystalline silicon film 16 is patterned by theusual lithography and etching to form the gate electrodes 20 having theupper surfaces covered with the insulation film 36 and the etchingstopper film 22.

Then, phosphorus ions, for example, are implanted into the siliconsubstrate 10 with the gate electrodes 20 as a mask to form the impuritydiffused layers 24, 26 (FIG. 5B).

Subsequently, a silicon oxide film is deposited on the entire surfaceby, e.g., CVD method., and then the surface of the silicon oxide film ispolished by, e.g., CMP method until the etching stopper film 22 isexposed, to form the inter-layer insulation film 28 buried between thegate electrodes 20 (FIG. 5C).

Then, a photoresist 46 for forming the contact holes for exposing theimpurity diffused layers 24, 26 is formed on the inter-layer insulationfilm 28 by the usual lithography technique.

Then, the inter-layer insulation film 28 is anisotropically etched byusing the photoresist 46 as a mask, and the etching stopper film 22formed on the gate electrodes 20 to form the contact holes 30, 40 openedon the impurity diffused layers 24, 26 (FIG. 6A).

The semiconductor device and the method for fabricating thesemiconductor device according to the present embodiment ischaracterized by a pattern of the photoresist 46.

It is possible that the photoresist 46 has respective openings on theimpurity diffused layer 24 and the impurity diffused layer 26, but whenthe device is much micronized, there is a risk that the hole patternopened on the impurity diffused layer 24 and the hole pattern opened onthe impurity diffused layer 26 are so near each other that thelithography of the photoresist itself may become impossible.

However, in the semiconductor device and the method for fabricating thesemiconductor device according to the present embodiment, the etchingstopper film 22 is formed, covering the upper surfaces of the gateelectrodes 20, and the surface of the etching stopper film 22 and thesurface of the inter-layer insulation film 28 are substantially flushwith each other, whereby by forming the photoresist 46 having theopening which includes the impurity diffused layers 24, 26 adjacent toeach other with the gate electrodes 20 disposed therebetween andcovering the gate electrodes 20, three contact holes for exposing theimpurity diffused layers 24, 26 can be opened by self-alignment with thegate electrodes 20 while the surface of the substrate is retained flat.

Thus, according to the present embodiment, as exemplified in FIG. 3B, itis not necessary that the photoresist 46 has fine hole patterns, whichfacilitates the lithography step for forming the photoresist 46.Retaining the surface of the substrate flat provides conveniences inlater steps of forming metallization from the impurity diffused layers24, 26.

As is in the semiconductor device according to the first embodiment andthe method for fabricating the same, the surface of the etching stopperfilm 22 is flat, which enables the contact holes 30, 40 to be openedwhile suppressing film thickness decrease of the etching stopper film 22in etching the inter-layer insulation film 28.

Then, a silicon oxide film is deposited on the entire surface by, e.g.,CVD method, and then etched to form the sidewall insulation film 32 onthe side walls of the interlayer insulation film 28 (FIG. 53) and theside walls of the laminated film of the gate electrodes 20, theinsulation film 36 and the etching stopper film 22 (FIG. 6B).

The sidewall insulation film 32 is thus formed, whereby the gateelectrodes 20 are covered with the etching stopper film 22, theinsulation film 36 and the sidewall insulation film 32 without beingexposed in the contact holes 30, 40.

As in the semiconductor device according to the first embodiment and themethod for fabricating the semiconductor device, it is not necessary toopen the contact holes by self-alignment with the sidewall insulationfilm 32, which allows the sidewall insulation film 32 to be formed ofsilicon oxide film. Accordingly, in comparison with a conventionalsemiconductor device including the sidewall insulation film 32 ofsilicon nitride film, the transistor can have higher hot carrierimmunity.

Next, a phosphorus-doped polycrystalline silicon film is deposited onthe entire surface by, e.g., CVD method, and then the surface of thepolycrystalline silicon film is polished by, e.g., CMP method until thesurface of the etching stopper film 22 is exposed to leave thepolycrystalline silicon film in the contact holes 30, 40. Thus, a plug42 buried in the contact hole 30, and a plug 44 buried in the contacthole 40 are formed (FIG. 6C). Even when the reduction in the filmthickness takes place on part of the etching stopper film 22 during theetching process for forming the contact hole 30 and 40, the surface ofthe etching stopper film 22 can be planarized by simultaneouslypolishing the projected portion of the etching stopper film 22 duringCMP process for forming the plugs 42, 44.

As described above, according to the present embodiment, the gateelectrodes 20 having the surfaces covered with the etching stopper film22 are formed, then the inter-layer insulation film 28 is buried betweenthe gate electrodes 20, and next the contact holes 30, 40 are opened inthe inter-layer insulation film 28, whereby the contact holes 30, 40which are adjacent to each other with the gate electrodes 20therebetween can be opened by the use of the photoresist 46 having thesingle opening 38. As a result, the lithography step for forming thecontact holes 30, 40 can be simple. As in the semiconductor device andthe method for fabricating the same according to the first embodiment,fluctuation of the contact area due to lithographic disalignment can beeliminated.

Because the sidewall insulation film 32 is formed after the contactholes 30, 40 are opened, it is not necessary to open the contact holes30, 40 by self-alignment with the sidewall insulation film 32, whichallows the sidewall insulation film 32 to be formed of silicon oxidefilm. As a result, in comparison with a conventional semiconductordevice including the sidewall insulation film 32 formed of siliconnitride film, the transistor can have higher hot carrier immunity.

However, the sidewall insulation film may be formed of silicon nitridefilm.

In the present embodiment, the insulation film 36 and the etchingstopper film 22 are formed on the gate electrodes 20, but the insulationfilm 36 is not essential. In the present embodiment, the insulation film36 of silicon oxide film is provided between the gate electrodes 20 andthe etching stopper film 22 for a purpose of reducing inter-layerdielectric constant. That is, the insulation film on the gate electrodes20 is preferably thick to reduce parasitic capacitance, but the effectis made higher by using a laminated film with silicon oxide film, whosedielectric constant is lower, than by thickening the insulation film ofsilicon nitride film alone. Accordingly, the insulation film 36 is notnecessary in a case, for example, that influence of parasiticcapacitance is allowable, or the parasitic capacitance can besufficiently restrained by other means.

In the semiconductor device and the method for fabricating the sameaccording to the present embodiment is applied to the memory cellregions of a DRAM but is applicable to other semiconductor devices.

In the above-described first and second embodiments the contact holeswhich arrive at the semiconductor substrate are formed by self-alignmentbetween the gate electrodes, but the present invention is applicable notonly to contacts to semiconductor substrates but also to other contacts.The present invention is applicable to a case that a viahole whichreaches a first interconnection of a first metallization layer is formedbetween second interconnections of a second metallization layer byself-alignment.

That is, the present invention is applicable to opening contact holesarriving at a base substrate between conductor patterns formed adjacentto each other on the base substrate having a prescribed structure.

[A Third Embodiment]

The semiconductor device and the method for fabricating the sameaccording to a third embodiment of the present invention will beexplained with reference to FIGS. 7A-7B, 8A-8B, 9A-9E, 10A-10C, 11A-11D,12A-12C, 13A-13B and 14A-14B.

FIGS. 7A and 7B are plan views of the semiconductor device according tothe present embodiment, which shows a structure thereof. FIGS. 8A and 8Bare diagrammatic sectional views of the semiconductor device accordingto the present embodiment, which show the structure thereof. FIGS.9A-9E, 10A-10C, 11A-11D and 12A-12C are sectional views of thesemiconductor device according to the present embodiment in the steps ofthe method for fabricating the semiconductor device, which explain themethod. FIGS. 13A and 13B are plan views of a resist pattern for forminga bit line contact holes of the semiconductor device according to thepresent embodiment, and of the opened contact hole. FIGS. 14A and 14Bare plan views of a resist pattern for forming a storage electrodecontact hole of the semiconductor device according to the presentembodiment and of the opened contact hole.

The present embodiment shows an example in which the semiconductordevice and the method for fabricating the same according to the secondembodiment is applied to a DRAM.

First, the structure of the semiconductor device according to thepresent embodiment will be explained with reference to FIGS. 7A-7B and8A-8B. FIGS. 7A and 7B are plan views of the semiconductor deviceaccording to the present embodiment, which show the structure of thesemiconductor device. FIG. 8A is a diagrammatic sectional view along theline X-X′ in FIG. 7A. FIG. 8B is a diagrammatic sectional view along theline Y-Y′ in FIG. 7B.

A device isolation film 52 for isolating devices is formed, buried in asilicon substrate 50. A plurality of word lines 56 are formed, through agate insulation film 54, on the silicon substrate 50 with the deviceisolation film 52 formed on, extended vertically of the drawing andparallel with each other. An etching stopper film 58 is formed on theword lines 56. Impurity diffused layers 60, 62 are formed in the siliconsubstrate 50 on both sides of the word lines 56. The gate electrodesprovided by the word lines 56 and the impurity diffused layers 60, 62constitute transfer transistors. An inter-layer insulation film 64having substantially the same height as the etching stopper film 58 isburied between the word lines 56. A plurality of bit lines 74 are formedon the etching stopper film 58 and the inter-layer insulation film 64,extended transversely of the drawing and parallel with each other. Thebit lines 74 are connected to the impurity diffused layers 60 in placeswhere the bit lines intersect an active region defined by the deviceisolation film 52. A storage electrode 86 is formed on the impuritydiffused layers 62. An opposed electrode 90 is formed on the storageelectrode 86 through a dielectric film 88. The storage electrode 86, thedielectric film 88 and the opposed electrode 90 constitute a capacitor.

The semiconductor device according to the present embodiment ischaracterized in that in a DRAM comprising memory cells each thusincluding one transistor and one capacitor, the step of opening acontact hole for connecting the impurity diffused layer 60 to the bitlines 74, and the step of opening a contact hole for connecting theimpurity diffused layer 62 with the storage electrode 86 use theself-alignment contact used in the second embodiment.

The semiconductor device and the method for fabricating thesemiconductor device according to the present embodiment will bedetailed in accordance with the steps of the method for fabricating thesemiconductor device according to the present embodiment. FIGS. 9A-9Eand 10A-10C are sectional views of the semiconductor device according tothe present embodiment along the line X-X′ in FIG. 7A in the steps ofthe method for fabricating the same, and FIGS. 11A-11D and 12A-12C aresectional views of the semiconductor device along the line Y-Y′ in FIG.7B in the steps of the method for fabricating the same.

First, trenches are formed in regions to be the device isolation regionsin, e.g., a p-type silicon substrate 50 are formed by the usuallithography and etching.

Next, a silicon oxide film is deposited by, e.g., CVD method, and thenthe surface of the silicon oxide film is polished by, e.g., CMP methodto leave the silicon oxide film only in the trenches formed in thesilicon substrate 50. Thus, the device isolation film 52 is formed,buried in the silicon substrate 50.

The thus-formed device isolation film 52 is known as the so-calledtrench isolation. The device isolation film 52 may be formed by otherdevice isolation techniques, e.g., LOCOS method, but the use of theabove-described trench isolation technique enables the surface of thesubstrate to be retained flat, which provides various conveniences offacilitating burying plugs by polishing in later steps, etc.

Subsequently, the silicon substrate 50 with the device isolation film 52formed in is thermally oxidized to form the gate insulation film 54 of,e.g., an about 6 nm-thick.

Then, an about 100 nm-thick polycrystalline silicon film and an about100 nm-thick WSi (tungsten silicide) film are deposited on the gateinsulation film 54. The polycide film of the thus-depositedpolycrystalline silicon film and WSi film is to be the word lines 56.

Then an about 200 nm-thick silicon nitride film is deposited on thepolycide film by, e.g., CVD method. The silicon nitride film is to bethe etching stopper film for etching the inter-layer insulation film.

Subsequently, the laminated film of the silicon nitride film and thepolycide film is patterned by the usual lithography and etching to formthe word lines 56 of the polycide structure having the upper surfacecovered with the etching stopper film 58 formed of the silicon nitridefilm. The word lines 56 have, e.g., a 0.2 μm-line width and are spacedfrom each other by 0.2 μm. The word lines 56 are so formed that two ofthe word lines are extended in one active region.

Then, phosphorus ions, for example, are implanted into the siliconsubstrate 50 with the word lines 56 as a mask to form the impuritydiffused layers 60, 62 in the active region (FIGS. 9A, FIG. 11A). Forexample, phosphorus ions are implanted under conditions of a 30 keVacceleration energy and a 2×10¹³ cm⁻² dose to form the impurity diffusedlayers 60, 62.

Then, an about 50 nm-thick silicon oxide film and an about 200-nm BPSG(Boro-Phospho Silicate Glass) film are deposited on the entire surfaceby, e.g., CVD method, and then thermal treated for 10 minutes at 850° C.in a nitrogen atmosphere to reflow the BPSG film. The thus-formedsilicon oxide film and BPSG film are to be the inter-layer insulationfilm.

It is possible that the thermal oxidation is performed before growingthe silicon oxide film to form an about 2 nm-thick silicon oxide film onthe side walls of the word lines 56. It is preferable that the sidewallinsulation film is formed on the side walls of the word lines 56 and thegate electrodes of transistors for a peripheral circuit before thegrowth of the silicon oxide film, to form a high-concentrationsource/drain diffused layer of the peripheral circuit transistor.

Subsequently, the BPSG film and the silicon oxide film are polished by,e.g., CMP method until the etching stopper film 58 is exposed to leavethe silicon oxide film and the BPSG film only between the word lines 56.Thus, the inter-layer insulation film 64 is formed, buried between theword lines 56 (FIG. 9B, FIG. 11B).

A photoresist 66 for forming a contact hole for exposing the impuritydiffused layer 60 is formed on the inter-layer insulation film 64 by theusual lithography technique (FIG. 9C, FIG. 11C). As shown in FIG. 13A,the photoresist 66 has an opening 68 in a region where the bit lines andthe impurity diffused layer 60 are connected to each other. The opening68 can be extended over the word lines 56 because the etching stopperfilm 58 is disposed on the word lines 56.

Then, the inter-layer insulation film 64 is anisotropically etched withthe photoresist 66 and the etching stopper film 58 as a mask underconditions which allow the silicon nitride film to have a sufficientlylow etching rate to form the contact hole 70 opened on the impuritydiffused layer 60. As shown in FIG. 13B, by using the photoresist 66 andthe etching stopper film 58 as a mask, the contact hole 70 can be openedonly upon the impurity diffused layer 60. Any steps are not formed inthe contact hole 70.

Next, a thermal treatment follows at 800° C. in a dry oxygen atmospherefor oxidation by an about 3 nm-film thickness to recover the gateinsulation film 54 on the ends of the word lines 56 from etchingdamages.

Subsequently, an about 80 nm-thick silicon oxide film is deposited onthe entire surface by, e.g., CVD method and then is anisotropicallyetched to form the sidewall insulation film 72 on the side walls of thecontact holes 70 (FIG. 9D). The word lines 56 are covered with theetching stopper film 58 and the sidewall insulation film 72, and are notexposed in the contact hole 70.

By thus forming the sidewall insulation film 72, the sidewall insulationfilm 72 is formed on the side walls of the word lines 56 in an about 60nm-width, and a final size of the bit line contact hole 70 is about 0.08μm.

It is also possible that when the contact hole 70 is formed, theperipheral circuit transistor is exposed, and the highly dopedsource/drain diffused layer of the peripheral circuit is formed afterthe sidewall insulation film 72 is formed. Thus, the sidewall insulationfilm for forming the LDD structure of the peripheral circuit transistorand the sidewall insulation film 72 in the contact hole 70 can beconcurrently formed, which has a merit that the number of the steps canbe decreased.

Next, an about 50 nm-thick phosphorus-doped polycrystalline siliconfilm, an about 100 nm-thick WSi film and an about 200 nm-thick siliconnitride film are deposited by, e.g., CVD method.

It is preferable that the polycrystalline silicon film has a filmthickness which is above a half a size of a bit line contact hole 70. Afilm thickness of the polycrystalline silicon film is above a half 0.08μm which is a size of the bit line contact hole 70, whereby thepolycrystalline silicon film is completely buried in the contact holes70, and the surface of the substrate can be substantially flat.

The laminated film of the silicon nitride film, the WSi film and thepolycrystalline silicon film is patterned to form the bit lines 74 ofthe polycide structure having the upper surface covered with the etchingstopper film 76 formed of the silicon nitride film.

Then, an about 50 nm-thick silicon oxide film and an about 200 nm-thickBPSG film are deposited on the entire surface by, e.g., CVD method, andthen are thermal treated for 10 minutes at 850° C. in a nitrogenatmosphere to reflow the BPSG film. The thus-formed silicon oxide filmand the BPSG film are to be the inter-layer insulation film.

Next, the BPSG film and the silicon oxide film are polished by, e.g.,CMP method to leave the silicon oxide film and the BPSG film onlybetween the bit lines 74. The inter-layer insulation film 77 is thusformed, buried between the bit lines 74 (FIG. 9E, FIG. 11D).

Subsequently, a photoresist 78 for forming a contact hole for exposingthe impurity diffused layer 62 on the inter-layer insulation film 77 andthe etching stopper film 76 is formed by the usual lithography technique(FIG. 10A). As shown in FIG. 14A, the photoresist 78 has a patternhaving an opening 80 in a region where the storage electrode and theimpurity diffused layer 62 are connected to each other. The opening 80can be extended over the bit lines 74 because the etching stopper film76 is disposed on the bit lines 74. As shown in FIG. 14A, thephotoresist 78 can have a stripe pattern in which the region between theword lines 56 is covered alternately by the photoresist 78. The stripepattern of the photoresist 78 makes fine alignment and sizingunnecessary, which can simplify the lithography step.

The inter-layer insulation films 77, 64 are anisotropically etched withthe photoresist 78 and the etching stopper film 76 as a mask underconditions which allow the silicon nitride film to have a sufficientlylow etching rate to form the contact hole 82 opened on the impuritydiffused layer 62 (FIG. 12A). By using the photoresist 78 and theetching stopper film 76 as a mask, the contact hole 82 can be opened asshown in FIG. 14B.

Next, a thermal treatment follows at 800° C. in a dry oxygen atmospherefor oxidation by an about 3 nm-film thickness to recover the gateinsulation film 54 on the ends of the word lines 56 from etchingdamages.

Subsequently, an about 80 nm-thick silicon oxide film is deposited onthe entire surface by, e.g., CVD method and then is anisotropicallyetched to form the sidewall insulation film 84 on the side walls of thecontact holes 82 (FIG. 12B, FIG. 10B). The bit lines 74 are covered withthe etching stopper film 76 and the sidewall insulation film 84, and arenot exposed in the contact hole 82.

By thus forming the sidewall insulation film 84, the sidewall insulationfilm 84 is formed on the side walls of the bit lines 74 in an about 60nm-width, and a final size of the storage electrode contact hole 82 isabout 0.08 μm.

An about 1500 nm-thick phosphorus-doped polycrystalline silicon film isdeposited by, e.g., CVD method and is patterned by the usual lithographyto form the storage electrode 86 connected to the impurity diffusedlayer 62 through the contact hole 82. As shown in FIG. 7B, the storageelectrode 86 can be formed in the region between the bit lines 74.

Then, an about 4 nm-thick silicon nitride film is deposited by, e.g.,CVD method, and then is thermal-treated for 10 minutes at 800° C. in awet oxygen atmosphere to oxidize the surface of the silicon nitride filmto form the dielectric film 88 of the silicon oxynitride film of anabout 4 nm-thick converted to a thickness of the silicon oxide film.This dielectric film can provide an about 22 fF cell capacitance. Thecapacitor can have a reduced height by the use of a high dielectricfilm, such as tantalum oxide film or others.

Subsequently, an about 100 nm-thick phosphorus-doped polycrystallinesilicon film is deposited by, e.g., CVD method and is patterned by theusual lithography to make the opposed electrode 90 for the capacitor(FIG. 10C, FIG. 12C).

Thus, a DRAM comprising memory cells each including one transistor andone capacitor is constituted.

As described above, according to the present embodiment, the word linesor the bit lines having the surfaces covered with the etching stopperfilm are formed, then the inter-layer insulation film is buried betweenthe word lines or the bit lines, and then the contact holes are formedin the inter-layer insulation film, whereby the lithography step forforming the contact holes does not require fine hole patterns, andalignment can have large allowance. As a result, the lithography stepfor forming the contact holes can be simple.

The ends of the opening in the photoresist for forming the contact holesare extended over the word lines or the bit lines, whereby evendisalignment takes place in the lithography, no fluctuation takes placein a contact hole size.

The sidewall insulation film 72 is formed after the contact hole 70 isopened, whereby it is not necessary to open the contact hole 70 byself-alignment with the sidewall insulation film 72, which permits thesidewall insulation film 72 to be formed of silicon oxide film.Accordingly, in comparison with the conventional semiconductor deviceincluding the sidewall insulation film 72 formed of silicon nitridefilm, the transistor can have higher hot carrier immunity.

In the present embodiment, the method for fabricating the semiconductordevice according to the second embodiment is applied to the step offorming the bit line contact hole and the step of forming the storageelectrode contact hole, but may be applied to either of the steps.

[A Fourth Embodiment]

The semiconductor device and the method for fabricating the sameaccording to a fourth embodiment of the present invention will beexplained with reference to FIGS. 15, 16A-16D and 17A-17B. The samemembers of the semiconductor device according to the present embodimentand the method for fabricating the semiconductor device as thesemiconductor device and the method for fabricating the same accordingto the third embodiment shown in FIGS. 7A to 14B are represented by thesame reference numbers not to repeat or to simplify their explanation.

FIG. 15 is a diagrammatic sectional view of the semiconductor deviceaccording to the present embodiment, which shows a structure thereof.FIGS. 16A-16D and 17A-17B are sectional views of the semiconductordevice according to the present embodiment in the steps of the methodfor fabricating the same, which explain the fabrication method.

In the semiconductor device and the method for fabricating the sameaccording to the third embodiment, the etching stopper film 58 isdisposed directly on the word lines 56 to be used as the inter-layerinsulation film with respect to the above bit lines 74, etc. The etchingstopper film 76 is disposed directly on the bit lines 74 to be used asthe inter-layer insulation film with respect to the above opposedelectrode 90, etc. However, as described in the second embodiment,silicon nitride film used as the etching stopper film 58, 76 has highdielectric constant, and there is a risk that a parasitic capacitancebetween metallization layers may be larger.

The semiconductor device according to the present embodiment has astructure and the method fabricating the same which can reduce parasiticcapacitance between metallization layers.

First, the structure of the semiconductor device according to thepresent embodiment will be explained with reference to FIG. 15. Theplane layout of the semiconductor device according to the presentembodiment is the same as that the semiconductor device according to thethird embodiment shown in FIGS. 7A and 7B. FIG. 15 is a diagrammaticsectional view along the line X-X′ in FIG. 7A.

The semiconductor device according to the present embodiment ischaracterized in that the semiconductor device according to the thirdembodiment shown in FIG. 8A includes an insulation film 92 of a siliconoxide film between the word line 56 and the etching stopper film 58, andan insulation film 94 of a silicon oxide film between the bit line 74and the etching stopper film 76. That is, an inter-layer insulation filmfor insulating the word line 56 from the bit line 74 is formed of theetching stopper film 58 and the insulation film 92, and an inter-layerinsulation film for insulating the bit line 74 from the opposedelectrode 90 is formed of the etching stopper film 76 and the insulationfilm 94.

Because silicon oxide film forming the insulation films 92, 94 has alower dielectric constant than silicon nitride film forming the etchingstopper films 58, 76, in place of thickening the etching stopper films58, 76 to reduce parasitic capacitance, the etching stopper films 58, 76have film thicknesses which allow them to function as the stopper, andthe insulation films 92, 94 are disposed below the etching stopper films58, 76, whereby the parasitic capacitance can be reduced withoutextremely thickening the inter-layer insulation films.

Accordingly, the semiconductor device has this structure, whereby a bitline contact hole 70 and a storage electrode contact hole 82 havemitigated aspect ratios while the parasitic capacitance can be reduced.

Then, the method for fabricating the semiconductor device according tothe present embodiment will be explained with reference to FIGS. 16A-16Dand 17A-17B. FIGS. 16A-16D and 17A-17B are sectional views of thesemiconductor device according to the present embodiment in the steps ofthe method for fabricating the semiconductor device along the line X-X′in FIG. 7A.

First, trenches are formed by the usual lithography and etching inregions on, e.g., p-type silicon substrate 50 which are to be deviceisolation regions.

Then, a silicon oxide film is deposited by, e.g., CVD method, and thenthe surface of the silicon oxide film is polished to leave the siliconoxide film only in the trenches formed in the silicon substrate 50.Thus, a device isolation film 52 formed buried in the silicon substrate50 is formed.

Subsequently, the silicon substrate 50 with the device isolation film 52formed in is thermally oxidized to form the gate insulation film 54 of,e.g., an about 6 nm-thick on the surface of the silicon substrate 50.

Then, an about 10 nm-thick polycrystalline silicon film and an about 100nm-thick WSi film are deposited on the gate insulation film 54 by, e.g.,CVD method. The polycide film of the thus-deposited polycrystallinesilicon film and WSi film is to be word lines.

Next, the insulation film 92 of an about 200 nm-thick silicon oxide filmis deposited on the polycide film by, e.g., CVD method.

Subsequently, an about 50 to 100 nm-thick silicon nitride film isdeposited on the insulation film 92 by, e.g., CVD method. The siliconnitride film is to be the etching stopper film 58 used in etching theinter-layer insulation film.

The thus-formed insulation film 92 and silicon nitride film function tobe finally the inter-layer insulation film for insulating the word lines56 from the bit lines 74. In the present embodiment the insulation film92 is formed of silicon oxide film having a low dielectric constant,whereby a low inter-layer capacitance can be obtained.

The laminated film of the silicon nitride film, the insulation film 92and the polycide film is patterned by the usual lithography and etchingto form the word lines 56 of polycide structure having the upper surfacecovered with the etching stopper film 58 of silicon nitride film and theinsulation film 92.

Then, phosphorus ions, for example, are implanted into the siliconsubstrate 50 with the word lines 56 as a mask to form impurity diffusedlayers 60, 62 in an active region (FIG. 16A).

Subsequently, the inter-layer insulation film 64, the bit line contacthole 70 and the sidewall insulation film 72 are formed in the same wayas in the semiconductor device according to, e.g., the third embodimentand the method for fabricating the same shown in FIGS. 9B-9D, and FIGS.11B-11C (FIGS. 16A-16D).

Then, an about 50 nm-thick phosphorus-doped polycrystalline siliconfilm, an about 100 nm-thick WSi film, the insulation film 94 of an about100 nm-thick silicon oxide film, and an about 50 to 100 nm-thick siliconnitride film are continuously deposited by, e.g., CVD method.

The thus-formed insulation film 94 and silicon nitride film function tobe finally the inter-layer insulation film for insulating the bit lines74 from the opposed electrode 90. In the present embodiment, theinsulation film 94 is formed of silicon oxide film having a lowdielectric constant, whereby a low inter-layer capacitance can beobtained.

Then, the laminated film of the silicon nitride film, the insulationfilm 94, the WSi film and the polycrystalline silicon film is patternedby the usual lithography and etching to form the bit lines 74 of thepolycide structure having the upper surfaces covered with the etchingstopper film 76 of the silicon nitride film and the insulation film 94(FIG. 17A).

A capacitor connected to the impurity diffused layer 62 is formed in thesame way as in the semiconductor device and the method for fabricatingthe same according to, e.g., the third embodiment shown in FIGS. 10A-10Cand FIGS. 12A-12C, and a DRAM comprising memory cells each including 1transistor and 1 capacitor is formed (FIG. 17B).

As described above, according to the present embodiment, the insulationfilm 92 of silicon oxide film is disposed between the etching stopperfilm 58 and the word lines 56, and the insulation film 94 of siliconoxide film is disposed between the etching stopper film 76 and the bitlines 74, whereby parasitic capacitance between metallization layers canbe reduced.

To the end of achieving the same inter-layer capacitance, in the presentembodiment the inter-layer insulation film can be thinner in comparisonwith a case that the inter-layer insulation film is formed of theetching stopper film alone of silicon nitride film, whereby the bit linecontact hole 70 and the storage electrode contact hole 82 can havesmaller aspect ratios. This facilitates formation of the contact holes.

[A Fifth Embodiment]

The semiconductor device and the method for fabricating the sameaccording to a fifth embodiment of the present invention will beexplained with reference to FIGS. 18, 19A-19D and 20A-20C. The samemembers of the present embodiment as the semiconductor device and themethod for fabricating the same according to the third and the fourthembodiments of the present invention shown in FIGS. 7A-17B arerepresented by the same reference numbers not to repeat or to simplifytheir explanation.

FIG. 18 is a diagrammatic sectional view of the semiconductor deviceaccording to the present embodiment, which shows a structure thereof.FIGS. 19A-19D and 20A-20C are sectional views of the semiconductordevice according to the present embodiment in the steps of the methodfor fabricating the same, which explain the method.

In the semiconductor device and the method for fabricating the sameaccording to the third and the fourth embodiments, the etching stopperfilm 76 covering the bit lines 74 are formed of silicon nitride film butare not essentially formed of an insulation film. The etching stopperfilm 76 may be formed of a conducting film, such as polycrystallinesilicon film or others, along as the conducting film can have etchingselectivity with respect to the inter-layer insulation film 64.

In the present embodiment, the semiconductor device and the method forfabricating the same according to the fourth embodiment includes theetching stopper film 76 covering the upper surface of the bit lines 74,which is formed of polycrystalline silicon film.

First, a structure of the semiconductor device according to the presentembodiment will be explained with reference to FIG. 18. The plan view ofthe semiconductor device according to the present embodiment is the sameas that of the semiconductor device according to the third embodimentshown in FIGS. 7A and 7B.

The semiconductor device according to the present embodiment is the samein the basic structure as the semiconductor device according to thefourth embodiment shown in FIG. 15 but is characterized in that theetching stopper film 76 covering the upper surfaces of the bit lines 74is provided by an etching stopper film 96 of polycrystalline siliconfilm.

Then, the method for fabricating the semiconductor device according tothe present embodiment will be explained with reference to FIGS. 19A-19Dand 20A-20C. FIGS. 19A-19D and 20A-20C are sectional views of thesemiconductor device according to the present embodiment along the lineY-Y′ in FIG. 7B in the steps of the method for fabricating thesemiconductor device.

First, in the same way as in the method for fabricating thesemiconductor device according to, e.g., the third embodiment shown inFIGS. 9A-9D and FIGS. 11A-11C a bit line contact holes 70 opened in aninter-layer insulation film 64, and a sidewall insulation film 72 areformed (FIGS. 19A-19C).

Subsequently, an about 50 nm-thick phosphorus-doped polycrystallinesilicon film, an about 100 nm-thick WSi film, an insulation film 94 ofan about 100 nm-thick silicon oxide film, and an about 50 to 100nm-thick polycrystalline silicon film are continuously deposited.

Subsequently, the laminated film of the polycrystalline silicon film,the insulation film 94, the WSi film and the polycrystalline siliconfilm is patterned by the usual lithography and etching to form bit lines74 of the polycide structure having the upper surfaces covered with theetching stopper film 96 of the polycrystalline silicon film and theinsulation film 94.

Then, an about 50 nm-thick silicon oxide film and an 200 nm-thick BPSGfilm are deposited on the entire surface by, e.g., CVD method and thenare thermally treated for 10 minutes at 850° C. in a nitrogen atmosphereto reflow the BPSG film. The thus-formed silicon oxide film and the BPSGfilm are films to be the inter-layer insulation film.

Then, the BPSG film and the silicon oxide film are polished by, e.g.,CMP method until the etching stopper film 96 is exposed to leave thesilicon oxide film and the BPSG film between the bit lines 74. Thus, theinter-layer insulation film 77 is formed, buried between the bit lines74 (FIG. 19D).

Subsequently, a photoresist 78 for opening a contact hole for exposingthe impurity diffused layer 62 is formed on the inter-layer insulationfilm 77 and the etching stopper film 96 by the usual lithographytechnique (see FIG. 10A). As shown in FIG. 14A, the photoresist 78 has apattern having an opening 80 in a region where the storage electrode andthe diffused layer 62 are connected to each other.

Then, the inter-layer insulation film 64 is anisotropically etched withthe photoresist 78 and the etching stopper film 96 as a mask underconditions which make an etching rate of the polycrystalline siliconfilm sufficiently low to form the contact hole 82 opened on the impuritydiffused layer 62 (FIG. 20A).

Next, a thermal treatment is performed at 800° C. in a dry oxygenatmosphere for oxidation by an about 3 nm-film thickness to recover thegate insulation film 56 on the ends of the word lines 56 from etchingdamages.

Subsequently, an about 80 nm-thick silicon oxide film is deposited onthe entire surface by, e.g., CVD method and then anisotropically etchedto form the sidewall insulation film 84 on the side walls of the contacthole 82 (FIG. 20B).

Then, an about 1500 nm-thick phosphorus-doped polycrystalline siliconfilm is deposited by, e.g., CVD method and is patterned by the usuallithography to form the storage electrode 86 connected to the impuritydiffused layer 62 through the contact hole 82. At this time, the etchingstopper film 96 of the polycrystalline silicon film on the bit lines 74is concurrently removed. The etching stopper film 96 is left in a regionwhere the pattern of the bit lines 74 overlap the pattern of the storageelectrode 86.

Then, an about 4 nm-thick silicon nitride film is deposited by, e.g.,CVD method and then is thermal treated for 10 minutes at 800° C. in awet oxygen atmosphere to oxidize the surface of the silicon nitride filmto form a dielectric film 88 of a silicon oxynitride film of an about 4nm-thick converted to a thickness of the silicon oxide film.

Subsequently, an about 100 nm-thick phosphorus-doped polycrystallinesilicon film is deposited by, e.g., CVD method and is patterned by theusual lithography to form an opposed electrode 90 for the capacitor(FIG. 20C).

Thus, a DRAM comprising memory cells each including one transistor andone capacitor is constituted.

As described above, according to the present embodiment, the etchingstopper film 96 used in opening the storage electrode contact hole 82 isformed of a conducting film, such as polycrystalline silicon film toform the storage electrode contact hole 82 by the use of the contacthole forming technique of the second embodiment.

[A Sixth Embodiment]

The semiconductor device and the method for fabricating the sameaccording to a sixth embodiment of the present invention will beexplained with reference to FIGS. 21 and 22A-22E. The same members ofthe present embodiment as the semiconductor device and the method forfabricating the semiconductor device according to the third to the fifthembodiments shown in FIGS. 7A to 20C are represented by the samereference numbers not to repeat or to simplify their explanation.

FIG. 21 is a diagrammatic sectional view of the semiconductor deviceaccording to the present embodiment, which shows a structure thereof.FIGS. 22A-22E are sectional views of the semiconductor device accordingto the present embodiment in the steps of the method for fabricating thesame, which explain the method.

In the semiconductor device and the method for fabricating the sameaccording to the fifth embodiment, the etching stopper film 96 coveringthe bit lines 74 are formed of polycrystalline silicon film, but theetching stopper film formed of a conducting film, such aspolycrystalline silicon film, may be used as the etching stopper film 58covering the upper surfaces of the word lines 56.

In the present embodiment, the semiconductor device and the method forfabricating the same according to the fourth embodiment includes theetching stopper film 58 covering the upper surfaces of the word lines56, which is formed of polycrystalline silicon film.

First, the structure of the semiconductor device according to thepresent embodiment will be explained with reference to FIG. 21. The planview of the semiconductor device according to the present embodiment isthe same as that of the semiconductor device according to the thirdembodiment as shown in FIGS. 7A and 7B.

The semiconductor device according to the present embodiment is the samein the basic structure as the semiconductor device according to thefourth embodiment shown in FIG. 15 but is characterized in that theetching stopper film 58 covering the upper surfaces of the word lines 56is formed of the etching stopper film 98 of polycrystalline siliconfilm.

Next, the method for fabricating the semiconductor device according tothe present embodiment will be explained with reference to FIGS.22A-22E. FIGS. 22A-22E are sectional views of the semiconductor deviceaccording to the present embodiment along the line X-X′ in FIG. 7A inthe steps of the method for fabricating the semiconductor device, whichexplain the method.

First, trenches are formed, by the usual lithography and etching inregions of, e.g., a p-type silicon substrate 50 which are to be deviceisolation regions.

Then, a silicon oxide film is deposited by, e.g., CVD method, and thenthe surface of the silicon oxide film is polished to leave the siliconoxide film only in the trenches formed in the silicon substrate 50.Thus, a device isolation film 52 is formed, buried in the siliconsubstrate 50.

Subsequently, the silicon substrate 50 with the device isolation film 52formed in is thermally oxidized to form a gate insulation film 54 of,e.g., an about 6 nm-thick silicon oxide film on the surface of thesilicon substrate 50.

Then, an about 100 nm-thick polycrystalline silicon film and an about100 nm-thick WSi film are deposited on the gate insulation film 54 by,e.g., CVD method. The polycide film of the thus-depositedpolycrystalline silicon film and WSi film is to be word lines.

An insulation film 92 of an about 200 nm-thick silicon oxide film isdeposited on the polycide film by, e.g., CVD method.

Subsequently, a polycrystalline silicon film of an about 50 to 100nm-thick is deposited on the insulation film 92 by, e.g., CVD method.The polycrystalline silicon film is to be an etching stopper film 98used in etching an inter-layer insulation film.

Then, the laminated film of the polycrystalline silicon film, theinsulation film 92 and the polycide film is patterned by the usuallithography and etching to form the word lines 56 of the polycidestructure having the upper surfaces covered with the etching stopperfilm 98 of the polycrystalline silicon film and the insulation film 92.

Then, phosphorus ions, for example, are implanted into the siliconsubstrate 50 to form impurity diffused layers 60, 62 in an active region(FIG. 22A).

Subsequently, an about 50 nm-thick silicon oxide film and an about 200nm-thick BPSG film are deposited on the entire surface by, e.g., CVDmethod and then is thermal treated for 10 minutes at 850° C. in anitrogen atmosphere to reflow the BPSG film. The thus-formed siliconoxide film and BPSG film are to be the inter-layer insulation film.

Then, the BPSG film and the silicon oxide film are polished by, e.g.,CMP method until the etching stopper film 98 is exposed to leave thesilicon oxide film and the BPSG film only between the word lines 56.Thus, the inter-layer insulation film 64 is formed, buried between theword lines 56 (FIG. 22B).

Then, a photoresist 66 for forming a contact hole for exposing theimpurity diffused layer 60 is formed on the inter-layer insulation film64 by the usual lithography technique (FIG. 22C).

Subsequently, with the photoresist 66 and the etching stopper film 98 asa mask, the inter-layer insulation film 64 is anisotropically etchedunder conditions which allow the polycrystalline silicon film to have asufficiently low etching rate to form the contact hole 70 opened on theimpurity diffused layer 60.

Then, a thermal treatment is performed at 800° C. in a dry oxygenatmosphere for oxidation by an about 3 nm-thick to recover the gateinsulation film 54 on the ends of the word lines 56 from etchingdamages.

Then, an about 80 nm-thick silicon oxide film is deposited on the entiresurface by, e.g., CVD method and then anisotropically etched to form asidewall insulation film 72 on the side walls of the contact holes 70(FIG. 22D).

Subsequently, an about 50 nm-thick phosphorus-doped polycrystallinesilicon film, an about 100 nm-thick WSi film and an about 200 nm-thicksilicon nitride film are continuously deposited by, e.g., CVD method.

Then, the laminated film of the silicon nitride film, the WSi film andthe polycrystalline silicon film is patterned by the usual lithographyand etching to form bit lines 74 of the polycide structure having theupper surfaces covered with the etching stopper film 76 of the siliconnitride film. At this time, the etching stopper film 98 covering theupper surfaces of the word lines 56 is removed concurrently withpatterning of the bit lines 74. The etching stopper film 98 is left in aregion where the pattern of the bit lines 74 crosses the pattern of theword lines 56 (FIG. 22E).

Then, in the same way as in the usual DRAM fabrication method, acapacitor connected to the impurity diffused layer 62 is formed, and aDRAM comprising memory cells each including 1 transistor and 1 capacitoris constituted.

In the method for fabricating the semiconductor device according to thepresent embodiment, the etching stopper film 98 is absent between thebit lines 74 after the bit lines 74 are patterned. Accordingly, theself-aligned contact forming technique of the second embodiment isinapplicable to the step of opening a storage electrode contact hole,but the storage electrode contact hole can be opened by the alignment ofthe usual lithography technique.

In a case that plugs are used in a seventh embodiment which will bedescribed later, it is not necessary that the storage electrode contacthole is in self-aligned contact with the word lines 56. Accordingly, theabove-described partial removal of the etching stopper film 98 on theword lines 56 causes no inconvenience.

As described above, according to the present embodiment, even in a casethat the etching stopper film 98 used in opening the bit line contacthole 70 is formed of a conducting film, such as polycrystalline siliconfilm or others, the contact hole forming technique of the secondembodiment can be used in forming the bit line contact hole 70.

[A Seventh Embodiment]

The semiconductor device and the method for fabricating the sameaccording to a seventh embodiment of the present invention will beexplained with reference to FIGS. 23A-23B, 24A-24E, 25A-25C, 26A-26E,27A-27C, 28A-28B, 29A-29B and 30. The same members of the presentembodiment as the semiconductor device according to the third to thesixth embodiments and the method for fabricating the semiconductordevice shown in FIGS. 7A to 22E are represented by the same referencenumbers not to repeat or to simplify their explanation.

FIGS. 23A and 23B are diagrammatic sectional views of the semiconductordevice according to the present embodiment, which show a structurethereof. FIGS. 24A-24E, 25A-25C, 26A-26E and 27A-27C are sectional viewsof the semiconductor device according to the present embodiment in thesteps of the method for fabricating the same, which explain the method.FIGS. 28A and 28B are plan views of a resist pattern for forming a bitline contact hole of the semiconductor device according to the presentembodiment and of the opened contact hole. FIGS. 29A and 29B are planviews of a resist pattern for forming a storage electrode contact holeof the semiconductor device according to the present embodiment and ofthe opened contact hole. FIG. 30 is a plan view of a resist pattern forforming a bit line contact hole of a modification of the semiconductordevice according to the present embodiment.

In the semiconductor device according to the third to the sixthembodiment, the storage electrode contact hole 82 for exposing thesilicon substrate 10 is formed. However, the contact size becomesextremely small as the device is increasingly micronized, and thecontact hole have a higher aspect ratio, which consequently makes theetching of the contact hole itself difficult.

The semiconductor device and the method for fabricating the sameaccording to the present embodiment can suppress aspect ratio increaseof the contact holes.

First, the structure of the semiconductor device according to thepresent embodiment will be explained with reference to FIGS. 23A and23B. The plan view of the semiconductor device according to the presentembodiment is the same as that of the semiconductor device according tothe third embodiment shown in FIGS. 7A and 7B. FIG. 23A is a sectionalview of the semiconductor device according to the present embodimentalong the line X-X′ in FIG. 7A. FIG. 23B is a sectional view of thesemiconductor device according to the present embodiment along the lineY-Y′ in FIG. 7B.

As shown in FIGS. 23A and 23B, the semiconductor device according to thepresent embodiment is characterized in that plugs 104. 106 havingsubstantially the same height as an inter-layer insulation film 64 areformed respectively on the bottom of a bit line contact hole 70 and astorage electrode contact hole 82.

In accordance with the method for fabricating the semiconductor deviceaccording to the present embodiment, the semiconductor device and themethod for fabricating the same according to the present embodiment willbe detailed. FIGS. 24A-24E and 25A-25C are sectional views of thesemiconductor device according to the present embodiment along the lineX-X′ in FIG. 7A in the steps of the method for fabricating thesemiconductor device. FIGS. 26A-26E and 27A-27C are sectional views ofthe semiconductor device according to the present embodiment along theline Y-Y′ in FIG. 7B in the steps of the method for fabricating thesemiconductor device.

First, in the same way as in the method for fabricating thesemiconductor device according to, e.g., the third embodiment shown inFIGS. 9A-9B and FIGS. 11A-11B, the inter-layer insulation film 64 isburied between the word lines 56 (FIGS. 24A-24B and 26A-26B).

Then, contact holes for exposing impurity diffused layers 60, 62 areformed on the inter-layer insulation film 64 by the usual lithographytechnique (FIG. 24C). As shown in FIG. 28A, the photoresist 66 has apattern including an opening 68 in a region where bit lines 74 and theimpurity diffused layer 60 are connected to each other, and an opening100 in a region where a storage electrode 86 and the impurity diffusedlayer 62 are connected to each other.

The etching stopper film 58 is disposed on the word lines 56, whichallows the openings 68, 100 to be extended over the word lines 56.Accordingly, the photoresist 66 can have not only the pattern shown inFIG. 28A, but also the pattern exemplified in FIG. 30, in which theopening 68 and the opening 100 are connected to each other in a mesh.The mask pattern shown in FIG. 30 makes it unnecessary to form a finehole pattern, which simplifies the lithography step.

Subsequently, the inter-layer insulation film 64 is anisotropicallyetched with the photoresist 68 and the etching stopper film 58 as a maskunder conditions which permit the silicon nitride film to have asufficiently low etching rate to form the contact hole 70 opened on theimpurity diffused layer 60 and the contact hole 102 opened on theimpurity diffused layer 62. By the use of the photoresist 66 and theetching stopper film 58 as a mask, the contact holes 70, 102 are openedas shown in FIG. 28B.

Subsequently, a thermal treatment is performed at 800° C. in a dryoxygen atmosphere for oxidation by an about 3 nm-thick to recover thegate insulation film 54 on the ends of the word lines 56 from etchingdamages.

Then, an about 80 nm-thick silicon oxide film is deposited on the entiresurface by, e.g., CVD method and then anisotropically etched to form asidewall insulation film 72 on the side walls of the contact holes 70,102 (FIG. 24D, FIG. 26C).

Next, a phosphorus-doped polycrystalline silicon film is deposited onthe entire surface by, e.g., CVD method, and then the surface of thepolycrystalline silicon film is polished by, e.g., CMP method until thesurface of the etching stopper film 58 is exposed to leave thepolycrystalline silicon film in the contact holes 70, 102. Thus, a plug104 buried in the contact hole 70, and a plug 106 buried in the contacthole 102 are formed (FIG. 24E, FIG. 26D). The plug 104 plays a role ofelevating the bottom of the bit line contact, and the plug 106 plays arole of elevating the bottom of a storage electrode contact.

In the semiconductor device and the method for fabricating the sameaccording to the present embodiment, the surface of the etching stopperfilm 58 and the surface of the inter-layer insulation film 64 aresubstantially flush with each other to thereby retain flatness of thesurface of the substrate, which facilitates formation of the plugs 104,106 by polishing, such as CMP method or others.

In forming a metallization layer by the usual lithography in place ofthe polishing, the surface flatness of the substrate enables finepatterning without considering a problem of DOF (depth of focus).

Subsequently, a silicon oxide film is deposited on the entire surfaceby, e.g., CVD method to form an inter-layer insulation film 108 of thesilicon oxide film.

Then, a contact hole 110 is opened in the inter-layer insulation film108 on the plug 104 by the usual lithography and etching.

Then, an about 50 nm-thick phosphorus-doped polycrystalline siliconfilm, an about 100 nm-thick WSi film and an about 200 nm-thick siliconnitride film are continuously deposited.

Subsequently, the laminated film of the silicon nitride film, the WSifilm and the polycrystalline silicon film is patterned by the usuallithography and etching to form a bit line 74 of the polycide structurehaving the upper surface covered with the etching stopper film formed ofthe silicon nitride film. The bit line 74 is connected to the plug 104through a contact hole 110 formed in the inter-layer insulation film108.

Then, an about 50 nm-thick silicon oxide film and an about 200 nm-thickBPSG film are deposited on the entire surface by, e.g., CVD method andthen is thermal treated for 10 minutes at 850° C. in a nitrogenatmosphere to reflow the BPSG film. The thus-formed silicon oxide filmand the BPSG film are to be an inter-layer insulation film.

Then, the BPSG film and the silicon oxide film are polished by, e.g.,CMP method until the etching stopper film 76 is disposed to leave thesilicon oxide film and the BPSG film only between the bit lines 74.Thus, the inter-layer insulation film 77 buried between the bit lines 74is formed (FIG. 26E).

Subsequently, a photoresist 78 for forming a contact hole for exposingthe plug 106 is formed on the inter-layer insulation film 77 and theetching stopper film 76 by the usual lithography (FIG. 25A). Because ofthe etching stopper film 76 is formed on the bit line 74, an opening 80can be extended over the bit lines 74. As shown in FIG. 29A, a stripepattern covering a region between the word lines alternately by the bitlines 74 is applicable for the pattern of the photoresist 78.

Subsequently, with the photoresist 78 and the etching stopper film 76 asa mask, the inter-layer insulation film 77 is anisotropically etchedunder conditions which allow the silicon nitride film to have asufficiently low etching rate to form a contact hole 82 opened on theplug 106 (FIG. 27A). By the use of the photoresist 78 and the etchingstopper film 76 as a mask, the contact hole 82 is opened as shown inFIG. 29B.

Subsequently, an about 80 nm-thick silicon oxide film is deposited onthe entire surface by, e.g., CVD method and is anisotropically etched toform a sidewall insulation film 84 on the side walls of the contact hole82 (FIG. 25B, FIG. 27B).

Then, an about 1500 nm-thick phosphorus-doped polycrystalline siliconfilm is deposited by, e.g., CVD method and is patterned by the usuallithography to form a storage electrode 86 connected to the impuritydiffused layer 62 through the plug 106. The contact interconnecting thestorage electrode 86 and the impurity diffused layer 62 is elevated bythe plug 106. Accordingly, in the semiconductor device according to thepresent embodiment it is not necessary that the contact hole 82 has ahigh aspect ratio, which facilitates etching of the contact hole 82.

Then, an about 4 nm-thick silicon nitride film is deposited by, e.g.,CVD method and then is thermal treated for 10 minutes at 800° C. in awet oxygen atmosphere to oxidize the silicon nitride film, and adielectric film 88 of the silicon oxynitride film of an about 4 nm-thickconverted to a thickness of the silicon oxide film.

Subsequently, an about 100 nm-thick phosphorus-doped polycrystallinesilicon film is deposited by, e.g., CVD method and patterned by theusual lithography to form an opposed electrode 90 for the capacitor(FIG. 25C, FIG. 27C).

Thus, a DRAM comprising memory cells each including 1 transistor and 1capacitor is constituted.

As described above, according to the present embodiment, the contact forinterconnecting the bit lines 74 and the impurity diffused layer 60, andthe contact for interconnecting the storage electrode 86 and theimpurity diffused layer 62 are elevated by the plugs 104, 106, which thecontact holes 70, 82 can be easily opened.

In the present embodiment, the contact elevation is applied to thesemiconductor device and the method for fabricating the same accordingto the third embodiment, but is similarly applicable to thesemiconductor device according to the other embodiments and the methodfor fabricating the same.

[An Eighth Embodiment]

The semiconductor device and the method for fabricating the sameaccording to an eighth embodiment of the present invention will beexplained with reference to FIGS. 31A-31B, 32A-32E, 33A-33C, 34A-34D and35A-35C. The same members of the present embodiment as the semiconductordevice and the method for fabricating the same according to the third tothe seventh embodiments shown in FIGS. 7A-30 are represented by the samereference numbers not to repeat or to simplify their explanation.

FIGS. 31A and 31B are diagrammatic sectional views of the semiconductordevice according to the present embodiment. FIGS. 32A-32E, 33A-33C,34A-34D and 35A-35C are sectional view of the semiconductor deviceaccording to the present embodiment in the steps of the method forfabricating the same, which explain the method.

In the semiconductor device and the method for fabricating the sameaccording to the present embodiment, the self-aligned contact formingmethod is applied to formation of a bit line contact hole and a storageelectrode contact hole of the semiconductor device according to thethird embodiment and the method for fabricating the same.

First, a structure of the semiconductor device according to the presentembodiment will be explained with reference to FIGS. 31A and 31B. Theplan view of the semiconductor device according to the presentembodiment is the same as that of the semiconductor device according tothe third embodiment shown in FIGS. 7A and 7B. FIG. 31A is a sectionalview of the semiconductor device according to the present embodimentalong the line X-X′ in FIG. 7A. FIG. 31B is a sectional view of thesemiconductor device according to the present embodiment along the lineY-Y′ in FIG. 7B

A device isolation film 52 for isolating devices is formed, buried in asilicon substrate 50. A plurality of word lines 56 are formed through agate insulation film 54 on the silicon substrate 50 with the deviceisolation film 52 formed on, extended parallel with each othervertically of the sheet of the drawing. An etching stopper film 58 isformed on the word lines 56. Impurity diffused layers 60, 62 are formedin the silicon substrate 50 on both sides of the word lines 56. The gateelectrodes provided by the word lines 56, and the impurity diffusedlayers 60, 62 constitute a transfer transistor. An inter-layerinsulation film 64 is formed on the word lines 56. A plurality of bitlines 74 are formed on the inter-layer insulation film 64, extendedparallel with each other horizontally of the sheet of the drawing. Thebit lines 74 are connected to the impurity diffused layer 60 inpositions where the bit lines 74 intersect an active region defined bythe device isolation film 52. A storage electrode 86 is formed on theimpurity diffused layer 62. An opposed electrode 90 is formed on thestorage electrode 86 through a dielectric film 88. The storage electrode86, the dielectric film 88 and the opposed electrode 90 constitute acapacitor.

In a DRAM thus comprising memory cells each including 1 transistor and 1capacitor, the semiconductor device according to the present embodimentuses the self-aligned contact in the step of opening the contact holefor connecting the impurity diffused layer 60 to the bit lines 74 andthe step of opening the contact hole for connecting the impuritydiffused layer 62 to the storage electrode 86.

The semiconductor device and the method for fabricating the sameaccording to the present embodiment will be detailed in accordance withthe method for fabricating the semiconductor device according to thepresent embodiment. FIGS. 32A-32E and 33A-33C are sectional views of thesemiconductor device according to the present embodiment along the lineX-X′ in FIG. 7A in the steps of the method for fabricating thesemiconductor device, which explain the method. FIGS. 34A-34D and35A-35C are sectional views of the semiconductor device according to thepresent embodiment along the line Y-Y′ in FIG. 7B in the steps of themethod for fabricating the semiconductor device, which explain themethod.

First, trenches are formed in, e.g., a p-type silicon substrate 50 inregions to be device isolation regions by the usual lithography andetching.

Then, a silicon oxide film is deposited by, e.g., CVD method, and thenthe surface of the silicon oxide film is polished to be left only in thetrenches formed in the silicon substrate 50. Thus, the device isolationfilm 52 is formed, buried in the silicon substrate 50.

Subsequently, the silicon substrate 50 with the device isolation film 52formed on is thermally oxidized to form the gate insulation film 54 of,e.g., an about 6 nm-thick of silicon oxide film is formed on the surfaceof the silicon substrate 50.

Then, an about 100 nm-thick polycrystalline silicon film and an about100 nm-thick WSi film are deposited on the gate insulation film 54. Thepolycide film of the thus-deposited polycrystalline silicon film and theWSi film is to be the word lines.

Then, an about 200 nm-thick silicon nitride film is deposited on thepolycide film by, e.g., CVD method. The silicon nitride film is to bethe etching stopper film to be used in etching the inter-layerinsulation film.

Subsequently, the laminated film of the silicon nitride film and thepolycide film is patterned by the usual lithography and etching to formthe word lines 56 of the polycide structure having the upper surfacecovered with the etching stopper film 58 formed of the silicon nitridefilm.

Then, phosphorus ions, for example, are implanted into the siliconsubstrate 50 with the word lines 56 as a mask to form the impuritydiffused layers 60, 62 in an active region (FIG. 32A, FIG. 34A).Phosphorus ions are implanted under conditions of, e.g., a 30 keVacceleration energy and a 2×10¹³ cm⁻² dose to form the impurity diffusedlayers 60, 62.

Then, a silicon oxide film is deposited on the entire surface by, e.g.,CVD method, and then the surface of the silicon oxide film is polishedby, e.g., CMP method and planarized to form the inter-layer insulationfilm 64 of the silicon oxide film (FIG. 32B, FIG. 34B). The inter-layerinsulation film 64 can be also formed by forming a BPSG film on theentire surface by, e.g., CVD method and reflowing the thus-formed BPSGfilm.

Subsequently, a photoresist 66 for forming a contact hole for exposingthe impurity diffused layer 60 is formed on the inter-layer insulationfilm 64 by the usual lithography technique. As shown in FIG. 13A, thephotoresist 66 is formed so that the ends of an opening 68 are extendedover the word lines 56, whereby a size of the opening in the photoresist66 may be large, and a large alignment allowance can be obtained.

Then, the inter-layer insulation film 64 is anisotropically etched withthe photoresist 66 and the etching stopper film 58 as a mask underconditions which permit the silicon nitride film to have a sufficientlylow etching rate to form the contact hole 70 opened on the impuritydiffused layer 60 (FIG. 32C, FIG. 34C).

Subsequently, a thermal treatment is performed at 800° C. in a dryoxygen atmosphere for oxidation by an about 3 nm-thick to recover theends of the gate insulation film 54 from etching damages.

Then, an about 80 nm-thick silicon oxide film is deposited on the entiresurface by, e.g., CVD method and then is anisotropically etched to forma sidewall insulation film 72 on the side walls of the inter-layerinsulation film 64 in the contact hole 70 and the side walls of the wordlines 56 and of the etching stopper film 58 (FIG. 32D).

Then, an about 50 nm-thick phosphorus-doped polycrystalline siliconfilm, an about 100 nm-thick WSi film and an about 200 nm-thick siliconnitride film are continuously deposited by, e.g., CVD method.

Subsequently, the laminated film of the silicon nitride film, the WSifilm and the polycrystalline silicon film is patterned by the usuallithography and etching to form the bit lines 74 of the polycidestructure having the upper surface covered with the etching stopper film76 formed of the silicon nitride film (FIG. 32E).

Then, a silicon oxide film is deposited on the entire surface by, e.g.,CVD method, and the surface of the silicon oxide film is polished by,e-g., CMP method to be planarized to form the inter-layer insulationfilm 77 of the silicon oxide film (FIG. 32B, FIG. 34B). The inter-layerinsulation film 77 can be also formed by forming a BPSG film on theentire surface by, e.g., CVD method and reflowing the thus-formed BPSGfilm.

Then, a photoresist 78 for forming a contact hole for exposing theimpurity diffused layer 62, on the inter-layer insulation film 77 by theusual lithography (FIG. 33A). Because of the etching stopper film 76 onthe bit lines 74, the opening can be extended over the bit lines 74, andas shown in FIG. 14A, the stripe pattern in which the region between theword lines 56 is covered alternately by the bit lines can be formed. Thestripe pattern of the photoresist 78 makes fine alignment and sizingunnecessary, which simplifies the lithography step.

Then, the inter-layer insulation film 64 is anisotropically etched withthe photoresist 78 and the etching stopper film 76 as a mask underconditions which allows the silicon nitride film to have a sufficientlylow etching speed to form the contact hole 82 opened on the impuritydiffused layer 62 (FIG. 35A).

Subsequently, a thermal treatment is performed at 800° C. in a dryoxygen atmosphere for oxidation by an about 3 nm-thick to recover theends of the gate insulation film 156 from etching damages.

Then, an about 80 nm-thick silicon oxide film is deposited on the entiresurface by, e.g., CVD method and then anisotropically etched to form thesidewall insulation film 84 on the side walls of the contact hole 82 andof the inter-layer insulation film 77 (FIG. 33B, FIG. 35B).

Next, an about 1500 nm-thick phosphorus-doped polycrystalline siliconfilm is deposited by, e-g., CVD method and patterned by the usuallithography to form the storage electrode 86 connected to the impuritydiffused layer 62 through the contact hole 82. As exemplified in FIG.7B, the storage electrode 86 can be formed in the region between the bitlines 74.

In patterning for forming the storage electrode 86, it is necessary thatno etching residue is present on the steps of the inter-layer insulationfilm 77. In the method for fabricating the semiconductor deviceaccording to the present embodiment, however, the steps of theinter-layer insulation film 77 are smoothed by the sidewall insulationfilm 84 formed on the steps such as FIG. 33B, which facilitates removalthe etching residue in comparison with the removal from steep steps.

Subsequently, an about 4 nm-thick silicon nitride film is deposited by,e.g., CVD method, and then a thermal treatment is performed for 10minutes a 800° C. in a wet oxygen atmosphere to oxidize the surface ofthe silicon nitride film to form a dielectric film 88 of the siliconoxynitride film of an about 4 nm-thick converted to a thickness of thesilicon oxide film.

Then, an about 100 nm-thick phosphorus-doped polycrystalline siliconfilm is deposited by, e.g., CVD method and then patterned by the usuallithography to be the opposed electrode 90 for a capacitor (FIG. 33C,FIG. 35C).

Thus, a DRAM comprising memory cells each including 1 transistor and 1capacitor is constituted.

As described above, according to the present embodiment, the word linesor the bit lines having the surfaces covered with the etching stopperfilm, then the inter-layer insulation film extended over the etchingstopper film, and then a contact hole extended over the word lines orthe bit lines is formed in the inter-layer insulation film, whereby inthe lithography step of forming the contact hole it is not necessarythat the hole pattern is fine, and a large alignment allowance can beused. Thus, the lithography step of forming the contact hole can besimplified.

The opening in the photoresist for forming the contact hole is extendedover the word lines or the bit lines, whereby a size of the contact holedoes not vary even when disalignment takes place in the lithography.

The sidewall insulation film 72 is formed after the contact hole 70 isopened, whereby it is not necessary to open the contact hole 70 in thesidewall insulation film by self-alignment, which allows silicon oxidefilm to form the sidewall insulation film 72. Accordingly, in comparisonwith the conventional method in which the sidewall insulation film 72 isformed of silicon nitride film, the transistor can have improved hotcarrier immunity.

[A Ninth Embodiment]

The semiconductor device and the method for fabricating the sameaccording to a ninth embodiment of the present invention will beexplained with reference to FIGS. 36A-36B, 37A-37C, 38A-38B, 39A-39B,40A-40C, 41A-41B and 42A-42B. The same members of the present embodimentas the semiconductor device and the method for fabricating the sameaccording to the eighth embodiment shown in FIGS. 7A to 35C will berepresented by the same reference numbers not to repeat or to simplifytheir explanation.

FIGS. 36A and 36B are diagrammatic sectional views of the semiconductordevice according to the present embodiment, which show a structurethereof. FIGS. 37A-37C, 38A-38B, 39A-39B, 40A-40C, 41A-41B and 42A-42Bare sectional views of the semiconductor device according to the presentembodiment in the steps of the method for fabricating the same, whichexplain the method.

The third to the eighth embodiments of the semiconductor device and themethod for fabricating the same were DRAMs having the capacitors abovethe bit lines. However, the present invention is applicable to DRAMshaving bit lines above capacitors.

The present embodiment is one example of applying the present inventionto a DRAM having bit lines above capacitors.

First, the structure of the semiconductor device according to thepresent embodiment will be explained with reference to FIGS. 36A and36B. The plan view of the semiconductor device according to the presentembodiment is the same as that of the semiconductor device according tothe third embodiment shown in FIGS. 7A and 7B. FIG. 36A is adiagrammatic sectional view of the semiconductor device according to thepresent embodiment along the line X-X′ in FIG. 7A, and FIG. 36B is adiagrammatic sectional view of the semiconductor device according to thepresent embodiment along the line Y-Y′ in FIG. 7B.

A device isolation film 52 for isolating devices is formed, buried in asilicon substrate 50. On the silicon substrate 50 with the deviceisolation film 52 formed in, a plurality of word lines 56 are formedthrough a gate insulation film 54, extended parallel with each other andvertically of the sheet of the drawing. An etching stopper film 58 isformed on the word lines 56. Impurity diffused layers 60, 62 are formedin the silicon substrate 50 on both sides of the word lines 56. The gateelectrodes provided by the word lines 56, and the impurity diffusedlayers 60, 62 constitute a transfer transistor. An inter-layerinsulation film 64 having substantially the same height as the etchingstopper film 58 is buried between the word lines 56. An inter-layerinsulation film 112 is formed on the etching stopper film 58 and theinter-layer insulation film 64. In the inter-layer insulation film 112there are formed a contact conducting film 118, connected to theimpurity diffused layer 60 through a plug 104, which formed on an insidewall of a contact hole formed in the inter-layer insulation film 112,and a storage electrode 86 connected to the impurity diffused layer 60through a plug 106, which formed on an inside wall of a contact holeformed in the inter-layer insulation film 112. An opposed electrode 90is formed on the surface of the storage electrode 86 through adielectric film 88. An inter-layer insulation film 122 is formed on theopposed electrode 90. On the inter-layer insulation film 122 there areformed bit lines 74 connected to the impurity diffused layer 60 throughthe contact conducting film 118 and the plug 106. Thus, the storageelectrode 86, the dielectric film 88 and the opposed electrode 90constitute a capacitor.

Thus, a DRAM comprising memory cells each including 1 transistor and 1capacitor is constituted.

The semiconductor device and the method for fabricating the sameaccording to the present embodiment will be detailed in accordance withthe steps of the method for fabricating the semiconductor deviceaccording to the present embodiment. FIGS. 37A-37C, 38A-38B and 39A-39Bare sectional views of the semiconductor device according to the presentembodiment along the line X-X′ in FIG. 7A, which are in the steps of themethod for fabricating the same. FIGS. 40A-40C, 41A-41B and 42A-42B aresectional views of the semiconductor device according to the presentembodiment along the line Y-Y′ in FIG. 7B, which are in the steps of themethod for fabricating the same.

In the same way as in the method for fabricating the semiconductordevice according to the seventh embodiment, for example, shown in FIGS.24A-24D and FIGS. 26A-26D, the plug 104 connected to the impuritydiffused layer 60 and the plug 106 connected to the impurity diffusedlayer 62 are formed (FIG. 37A, FIG. 40A).

Then, an about 2 μm-thick silicon oxide film is deposited on the entiresurface by, e.g., CVD method, and the surface of the silicon oxide filmis polished by e.g., CMP method and planarized. Thus, the inter-layerinsulation film 112 of silicon oxide film is formed.

Then, a through-hole 114 and a through-hole 116 are formed in theinter-layer insulation film 112, opened respectively on the plug 104 andthe plug 106 (FIG. 37B, FIG. 40B).

Subsequently, an about 50 nm-thick highly phosphorus-dopedpolycrystalline silicon film is formed by, e.g., CVD method, and thepolycrystalline silicon film on the inter-layer insulation film 112 iscompletely removed by CMP method. Thus, the contact conducting film 118and the storage electrode 86 can be formed by self-alignmentrespectively in the through-hole 114 and the through-hole 116 (FIG. 37C,FIG. 40C).

Then, an about 4 nm-thick silicon nitride film is deposited by, e.g. CVDmethod and then thermally treated for 10 minutes at 800° C. in a wetoxygen atmosphere to oxidize the surface of the silicon nitride film toform the dielectric film 88 of a silicon oxynitride film of an about 4nm-thick converted to silicon oxide film.

Then, an about 100 nm-thick phosphorus-doped polycrystalline siliconfilm 120 is deposited by, e.g., CVD method (FIG. 38A, FIG. 41A).

Subsequently, a silicon oxide film is deposited by, e.g., CVD method toform the inter-layer insulation film 122 (FIG. 38B, FIG. 41B).

Then, the inter-layer insulation film 122 and the polycrystallinesilicon film 120 are patterned to form the opposed electrode 90 formedof the polycrystalline silicon film 120.

Then, a silicon oxide film is deposited on the entire surface by, e.g.,CVD method and then anisotropically etched to form the sidewallinsulation film 124 on the side walls of the inter-layer insulation film122 and of the opposed electrode 90 (FIG. 39A, FIG. 42A). At this time,the dielectric film 88 on the contact conducting film 118 is removed toexpose the contact conducting film 118.

Next, continuously an about 50 nm-thick titanium film is deposited by,sputtering, and an about 50 nm-thick TiN film and an about 200 nm-thicktungsten film are deposited by, e.g., CVD method. Then, the laminatedfilm of the W film/TiN film/Ti film is patterned by the usuallithography and etching to form the bit lines 74 (FIG. 38B, FIG. 42B).

Thus, a DRAM comprising memory cells each including 1 transistor and 1capacitor is constituted.

As described above, according to the present embodiment, by the use ofthe method for forming the self-aligned contact of the secondembodiment, a DRAM including the bit lines above the capacitors can bealso formed.

In the present embodiment, the DRAM is constituted based on the layoutof FIGS. 7A and 7B, and it is also possible to constitute the DRAM shownin FIG. 43, based on the layout of, e.g., FIGS. 3A and 3B. The DRAM ofFIG. 43 can be fabricated by the fabrication method according to thepresent embodiment by using the layout of FIGS. 3A and 3B.

The present embodiment is applied to the DRAM described in, e.g.,Japanese Patent Laid-Open Publication No. 274278/1996 filed by theapplicant of the present application but is applicable to devices ofother structures.

[A Tenth Embodiment]

The semiconductor device and the method for fabricating the sameaccording to a tenth embodiment of the present invention will beexplained with reference to FIGS. 44, 45A-45C and 46A-46C. The samemembers of the present embodiment as the semiconductor device accordingto the third to the ninth embodiments shown in FIGS. 7A to 43 and themethod for fabricating the same are represented by the same referencenumbers not to repeat or to simplify their explanation.

FIG. 44 is a diagrammatic sectional view of the semiconductor deviceaccording to the present embodiment, which shows a structure thereof.FIGS. 45A-45C and 46A-46C are sectional views of the semiconductordevice according to the present embodiment in the steps of the methodfor fabricating the same, which explain the method.

In the semiconductor device and the method for fabricating the sameaccording to the third to the ninth embodiments, DRAMs fabricated byusing the techniques for forming the self-aligned contacts of the firstor the second embodiment have been explained. Even by the use of themethod for fabricating the conventional semiconductor device shown inFIGS. 51A-51D, it is possible to make a photoresist size for opening thecontact holes large and make alignment allowance large.

The semiconductor device and the method for fabricating the sameaccording to the present embodiment can simplify lithography for theconventional self-aligned contact forming technique.

First, the structure of the semiconductor device according to thepresent embodiment will be explained with reference to FIG. 44. The planview of the semiconductor device according to the present embodiment isthe same as that of the semiconductor device according to the thirdembodiment shown in FIGS. 7A and 7B. FIG. 44 is a diagrammatic sectionalview of the semiconductor device according to the present embodimentalong the line X-X′ in FIG. 7A. The sectional view of the semiconductordevice according to the present embodiment along the line Y-Y′ in FIG.7B is the same as that of the semiconductor device according to thethird embodiment.

A device isolation film 52 for isolating devices is formed, buried in asilicon substrate 50. A plurality of word lines 56 are formed, through agate insulation film 54, on the silicon substrate 50 with the deviceisolation film 52 buried in, extended parallel with each other andvertically of the sheet of the drawing. The word lines 56 have the uppersurfaces covered with an etching stopper film 58 and the side wallscovered with a sidewall insulation film 126 etching characteristics ofwhich are substantially equal to those of the etching stopper film 58.Impurity diffused layers 60, 62 are formed in the silicon substrate 50on both sides of the word lines 56. The gate electrodes provided by theword lines 56, and the impurity diffused layers 60, 62 constitute atransfer transistor. An inter-layer insulation film 64 having asubstantially equal height as the etching stopper film 58 is buriedbetween the word lines 56. On the etching stopper film 58 and theinter-layer insulation film 64, there are formed a plurality of bitlines 74 extended parallel with each other and horizontally of the sheetof the drawing. The bit lines 74 are connected to the impurity diffusedlayer 60 at locations where the bit lines 74 intersect an active regiondefined by the device isolation film 52. A storage electrode 86 isformed on the impurity diffused layer 62. An opposed electrode 90 isformed on the storage electrode 86 through a dielectric film 88. Thus,the storage electrode 86, the dielectric film 88 and the opposedelectrode 90 constitute a capacitor.

Thus, a DRAM comprising memory cells each including 1 transistor and 1capacitor is constituted.

Then, the semiconductor device and the method for fabricating the sameaccording to the present embodiment will be detailed in accordance withthe method for fabricating the semiconductor device according to thepresent embodiment. FIGS. 45A-45C and 46A-46C are sectional views of thesemiconductor device according to the semiconductor device along theline X-X′ in FIG. 7A in the steps of the method for fabricating thesame.

First, trenches are formed in regions of, e.g., a p-type siliconsubstrate 50, where a device isolation film is formed are formed by theusual lithography and etching.

Then, a silicon oxide film is deposited by, e.g., CVD method, and thenthe surface of the silicon oxide film is polished to leave the siliconoxide film only in the trenches formed in the silicon substrate 50.Thus, the device isolation film 52 is formed, buried in the siliconsubstrate 50.

Subsequently, the silicon substrate 50 with the device isolation film 52formed in is thermally oxidized to form the gate insulation film 54 of,e.g., an about 6 nm-thick silicon oxide film on the surface of thesilicon substrate 50.

Then, an about 100 nm-thick polycrystalline silicon film and an about100 nm-thick WSi film are formed on the gate insulation film 54 by,e.g., CVD method. The polycide film of the thus-depositedpolycrystalline silicon film and WSi film are to be the word lines.

Then, an about 200 nm-thick silicon nitride film is deposited on thepolycide film by, e.g., CVD method. The silicon nitride film is to bethe etching stopper film to be used in etching the inter-layerinsulation film.

Subsequently, the laminated film of the silicon nitride film and thepolycide film is patterned by the usual lithography and etching to formthe word lines 56 of the polycide structure having the upper surfacecovered with the etching stopper film 58 of the silicon nitride film.

Then, with the word lines 56 as a mask phosphorus ions, for example, areimplanted into the silicon substrate 50 to form the impurity diffusedlayers 60, 62 in an active region. The ions are implanted underconditions of, e.g., a 30 keV acceleration energy and a 2×10₁₃ cm⁻²dose.

Next, an about 80 nm-thick silicon nitride film is deposited on theentire surface by, e.g., CVD method and then anisotropically etched toform the sidewall insulation film 126 on the side walls of the wordlines 56 and the etching stopper film 58 (FIG. 45A). The word lines 56are completely covered with the etching stopper film 58 and the sidewallinsulation film 126.

Subsequently, an about 50 nm-thick silicon oxide film and an about 200nm-thick BPSG film are deposited on the entire surface by, e.g., CVDmethod and then is polished by, e.g., CMP method until the etchingstopper film 58 is exposed on the surface to form the inter-layerinsulation film 64 buried between the word lines 56 (FIG. 45B).

Then, a photoresist 66 for forming a contact hole for exposing theimpurity diffused layer 60 on the inter-layer insulation film 64 by theusual lithography technique (FIG. 45C). Because of the etching stopperfilm 58 on the word lines 56, an opening 68 can be extended over theword lines 56. Accordingly, the photoresist 66 can have the same patternas that used in the method for fabricating the semiconductor deviceaccording to, e.g., the third embodiment shown in FIG. 13A. As a result,the lithography for forming the photoresist 66 can have a largealignment allowance and have a large pattern size, which simplifies thelithography.

Subsequently, with the etching stopper film 58 and the sidewallinsulation film 128 as a mask, the inter-layer insulation film 64 isanisotropically etched under conditions which allows the silicon nitridefilm has a sufficiently low etching rate to form a contact hole 70opened on the impurity diffused layer 60 (FIG. 46A). The contact hole 70is opened as shown in FIG. 13B by using the photoresist 66 and theetching stopper film 58 as a mask.

Then, an about 50 nm-thick phosphorus-doped polycrystalline siliconfilm, an about 100 nm-thick WSi film and an about 200 nm-thick siliconnitride film are continuously deposited by, e.g., CVD method.

Then, the laminated film of the silicon nitride film the WSi film andthe polycrystalline silicon film is patterned by the usual lithographyand etching to form bit lines 74 of the polycide structure having theupper surface covered with the etching stopper film 76 of the siliconnitride film (FIG. 46C).

Subsequently, in the same way as in the method for fabricating thesemiconductor device according to, e.g., the third embodiment shown inFIG. 10A to FIG. 10C, a capacitor comprising the storage electrode 86,the dielectric film 88 and the opposed electrode 90 is formed (FIG.46C).

Thus, a DRAM comprising memory cells each including 1 transistor and 1capacitor is constituted.

As described above, according to the present embodiment, even in a casethat the structure used in the conventional self-aligned contact isused, a photoresist size for opening the contact holes can be large, anda large disalignment allowance is possible. Accordingly, the lithographystep of opening the bit line contact hole can be simple.

In the present embodiment, the etching stopper film 58 is formeddirectly on the word lines 56, but as in the semiconductor deviceaccording to the fourth embodiment, the insulation film 94 of lowdielectric constant is disposed between the word lines 56 and theetching stopper film 58.

1: A method for fabricating a semiconductor device comprising: a firstconducting film forming step of forming on a base substrate a firstconducting film including a plurality of conductor patterns adjacent toeach other, and having a upper surface thereof covered with an etchingstopper film; a first insulation film forming step of forming a firstinsulation film buried between said a plurality of conductor patterns; acontact hole forming steps of etching the first insulation film with theetching stopper film as a mask to form a contact hole which reaches thebase substrate between the conductor patterns and an end of which isdefined by the conductor patterns; and a sidewall insulation filmforming steps of forming a sidewall insulation film on side walls of thefirst conducting film and the etching stopper film in the contact hole.2: A method for fabricating a semiconductor device according to claim 1,wherein in the contact hole forming step the first insulation film isetched with a photoresist having an opening extended over said aplurality of conductor patterns and the etching stopper film as a maskto form a plurality of the contact holes in the opening. 3: A method forfabricating a semiconductor device according to claim 1, furthercomprising before the first conducting film forming step, a deviceisolation film forming step of forming a device isolation film buried inthe base substrate. 4: A method for fabricating a semiconductor deviceaccording to claim 2, further comprising before the first conductingfilm form step, a device isolation film forming step of forming a deviceisolation film buried in the base substrate. 5: A method for fabricatinga semiconductor device comprising: a word line forming step of formingon a semiconductor substrate a plurality of word lines extended in afirst direction of having upper surfaces thereof covered with an etchingstopper film; a first insulation film forming step of forming a firstinsulation film on the etching stopper film and the semiconductorsubstrate; a contact hold forming step of forming in the firstinsulation film a contact hole which reaches the semiconductor substratebetween the word lines, and an end of which is positioned on the etchingstopper film on the word lines; a sidewall insulation film forming stepof forming a sidewall insulation film on side walls of the word linesand of the etching stopper film in the contact hole; and a bit lineforming step of forming on the first insulation film a plurality of bitlines extended in a second direction which intersects the firstdirection and connected to the semiconductor substrate through thecontact hole. 6: A method for fabricating a semiconductor devicecomprising: a word line forming step of forming on a semiconductorsubstrate a plurality of word lines extended in a first direction ofhaving upper surfaces thereof covered with an etching stopper film; afirst insulation film forming step of forming a first insulation filmburied between the word lines; a contact hole forming step of etchingthe first insulation film with the etching stopper film as a mask toform a contact hole which reaches the semiconductor substrate betweenthe word lines and an end of which is defined by the word lines; asidewall insulation film forming step of forming a sidewall insulationfilm on side walls of the word lines and the etching stopper film in thecontact hole; and a bit line forming step of forming on the firstinsulation film a plurality of bit lines extended in a second directionwhich intersects the first direction and connected to the semiconductorsubstrate through the contact hole. 7: A method for fabricating asemiconductor device comprising: a word line forming step of forming ona semiconductor substrate a plurality of word lines extended in a firstdirection and having upper surfaces thereof covered with an etchingstopper film; a sidewall insulation film forming step of formingsidewall insulation film having etching characteristics substantiallyequal to those of the etching stopper film on side walls of the wordlines and of the etching stopper film; a first insulation film formingstep of forming a first insulation film buried between the word lineswith the sidewall insulation film formed on; a contact hole forming stepof etching the first insulation film with the etching stopper film andthe sidewall insulation film as a mask to form a contact hole whichreaches the semiconductor substrate between the word lines and an end ofwhich is defined by the sidewall insulation film; and a bit line formingstep of forming on the first insulation film a plurality of bit linesextended in a second direction which intersects the first direction andconnected to the semiconductor substrate through the contact hole. 8: Amethod for fabricating the semiconductor device according to claim 6,wherein in the contact hole forming step, the first insulation film isetched with a photoresist including an opening extended over the wordlines, and the etching stopper film as a mask to form a plurality of thecontact holes in the opening. 9: A method for fabricating thesemiconductor device according to claim 7, wherein in the contact holeforming step, the first insulation film is etched with a photoresistincluding an opening extended over the word lines, and the etchingstopper film as a mask to form a plurality of the contact holes in theopening. 10: A method for fabricating the semiconductor device accordingto claim 5, further comprising before the bit line forming step, a plugforming step of forming a plug buried in the contact hole. 11: A methodfor fabricating the semiconductor device according to claim 6, furthercomprising before the bit line forming step, a plug forming step offorming a plug buried in the contact hole. 12: A method for fabricatingthe semiconductor device according to claim 7, further comprising beforethe bit line forming step, a plug forming step of forming a plug buriedin the contact hole. 13: A method for fabricating a semiconductor devicecomprising: a word line forming step of forming on a semiconductorsubstrate a plurality of word lines extended in a first direction; afirst insulation film forming step of forming a first insulation film onthe semiconductor substrate with the work lines formed on; a bit lineforming step of forming on the first insulation film a plurality of bitlines extended in a second direction which intersects the firstdirection and having upper surfaces thereof covered with an etchingstopper film; a second insulation film forming step of forming a secondinsulation film on the etching stopper film and the first insulationfilm; a contact hole forming step forming in the second insulation filma contact hole which is formed between the bit lines and an end of whichis positioned on the etching stopper film on the bit lines; a sidewallinsulation film forming step of forming a sidewall insulation film onside walls of the bit lines and of the etching stopper film in thecontact hole; and a capacitor forming step of forming on the secondinsulation film a capacitor having one electrode connected to thesemiconductor substrate through the contact hole. 14: A method forfabricating a semiconductor device comprising: a word line forming stepof forming on a semiconductor substrate a plurality of word linesextended in a first direction; a first insulation film forming step offorming a first insulation film on the semiconductor substrate with theword lines formed on; a bit line forming step of forming on the firstinsulation film a plurality of bit lines extended in a second directionwhich intersects the first direction and having upper surface thereofcovered with an etching stopper film; a second insulation film formingstep of forming a second insulation film buried between the bit lines; acontact hole forming step of etching the second insulation film with theetching stopper film as a mask to form a contact hole which is formed onbetween the bit lines and an end of which is defined by the bit lines; asidewall insulation film forming step of forming a sidewall insulationfilm on side walls of the bit lines and of the etching stopper film inthe contact hole; and a capacitor forming step of forming on the secondinsulation film a capacitor having one electrode connected to thesemiconductor substrate through the contact hole. 15: A method forfabricating a semiconductor device according to claim 13, wherein incontact hole forming step, the second insulation film is etched with aphotoresist having a pattern which alternately covers a region betweenthe word lines, and the etching stopper film as a mask to form aplurality of the contact holes. 16: A method for fabricating asemiconductor device according to claim 14, wherein in contact holeforming step, the second insulation film is etched with a photoresisthaving a pattern which alternately covers a region between the wordlines, and the etching stopper film as a mask to form a plurality of thecontact holes. 17: A method for fabricating a semiconductor deviceaccording to claim 13, wherein in the contact hole forming step, thefirst insulation film and the second insulation film are etched to forma contact hole which reaches the semiconductor substrate and an end ofwhich is defined by the bit lines and the word lines. 18: A method forfabricating a semiconductor device according to claim 14, wherein in thecontact hole forming step, the first insulation film and the secondinsulation film are etched to form a contact hole which reaches thesemiconductor substrate and an end of which is defined by the bit linesand the word lines. 19: A method for fabricating a semiconductor deviceaccording to claim 13, wherein in the bit line forming step, the etchingstopper film is formed of a conductor; and in the capacitor forming stepthe etching stopper film is processed in the same pattern as said oneelectrode of the capacitor. 20: A method for fabricating a semiconductordevice according to claim 14, wherein in the bit line forming step, theetching stopper film is formed of a conductor; and in the capacitorforming step the etching stopper film is processed in the same patternas said one electrode of the capacitor.